M5M4V64S20ATP-12 查看數據表（PDF） - MITSUBISHI ELECTRIC

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M5M4V64S20ATP-12

64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM

MITSUBISHI ELECTRIC  

SDRAM (Rev.1.3)

Mar98

MITSUBISHI LSIs

M5M4V64S20ATP-8A,-8L,-8, -10L, -10

64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM

[ Read Interrupted by Precharge ]

Burst read operation can be interrupted by precharge of the same bank . READ to PRE interval is mini-

mum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. As a result,

READ to PRE interval determines valid data length to be output. The figure below shows examples of

BL=4.

Read Interrupted by Precharge (BL=4)

CLK

CL=3

Command

DQ

Command

DQ

Command

DQ

READ

PRE

Q0 Q1 Q2

READ

PRE

Q0 Q1

READ PRE

Q0

CL=2

Command

DQ

Command

DQ

Command

DQ

READ

PRE

Q0 Q1 Q2

READ

PRE

Q0 Q1

READ PRE

Q0

MITSUBISHI ELECTRIC

20

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