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NJU3504FA1 查看數據表(PDF) - Japan Radio Corporation

零件编号
产品描述 (功能)
比赛名单
NJU3504FA1
JRC
Japan Radio Corporation  JRC
NJU3504FA1 Datasheet PDF : 60 Pages
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NJU3504
s INPUT OUTPUT PORT
The NJU3504 prepares 25 Input-Output lines and 10 dual-function lines for the interface to an external
application circuit. All lines are assigned to each Peripheral Register.
Data reading operation from the peripheral register can input the actual signals through the input
terminal. Data writing operation to the peripheral register can output the actual signals through the output
terminal.
[PORT FUNCTION TABLE]
PORT NAME
FUNCTION
INPUT/OUTPUT
PORTA, PORTB
Input / Output port
Programmable Input / Output PORT(4-bit).
PORTC PORTH
PORTI
PORTJ(PJ0)
PORTJ(PJ1)
Input / Output port
Input port or AIN0 AIN3
Input port or VREF
Input port or ADCK
Input / Output selectable ports by the mask option.
Input
Input
Input
PORTK(PK0)
Input port or EXTI
Input
PORTK(PK1)
Input port or CNTI
Input
PORTL(PL0)
Output Port or SDO
Output
PORTL(PL1)
Input / Output port or SDI(O) Input / Output selectable ports by the mask option.
Note1) PORTG is not prepared on the NJU3504L(SDIP package).
Note2) Pull-up resistance is selected by the mask option.(refer !INPUT OUTPUT TERMINAL TYPE)
(1) INPUT OUTPUT PORT
PORTA(PA0 PA3)
PORTA is a 4-bit programmable input-output PORT. It is set as the output when LSB of the
programmable input/output control register(PHY29) is set to “1”, and is set as the input when LSB of
PHY29 is set to “0”. When the PORT is set as the output, the 4-bit signals are output through the output
terminals by writing data into the peripheral register assigned for PORTA(PHY17). PHY17 as the output
register should be written the output data before the PORTA is set as the output by PHY29, because the
conditions of the output terminals are unknown while the output data is not written in PHY17. When this
PORT is set as the input, the 4-bit external signals are gotten directly through the input terminals by
reading data from PHY17. PHY17 can be written or read independent of the state of PHY29 as the input
or output.
Though the output circuit is Nch open drain type, the C-MOS input buffer is connected to the same
terminal. Therefore, the operating current of the chip by the short circuit current when the middle level
voltage between VDD and VSS is input to this terminal.
PORTA is set as the input in accordance with the state of PHY29 set to “0” on the “RESET” operation.
[READING PORTA INPUT DATA (PHY17)]
(MSB) 3
2
1
0
PHY17
PA3
PA2
PA1 PA0
(LSB)
PORTA Input Data
[WRITING PORTA OUTPUT DATA (PHY17)]
(MSB) 3
2
1
0
PHY17 PA3 PA2 PA1 PA0
(LSB)
PORTA Output Data
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