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NJU3504FA1 查看數據表(PDF) - Japan Radio Corporation

零件编号
产品描述 (功能)
比赛名单
NJU3504FA1
JRC
Japan Radio Corporation  JRC
NJU3504FA1 Datasheet PDF : 60 Pages
First Prev 51 52 53 54 55 56 57 58 59 60
NJU3504
2)Edge Detector Selection
When the PORTH(PHY24) is set as the input, PH1 terminal operates as Edge Detector terminal. The result
of the edge detection is set into bit(b2) of PORTH(PHY24).
The polarity of the edge, rising as ”low to high or high to low”, is selected by the mask option.
Rising edge
Falling edge
3)The data order(MSB, LSB) of the Serial Interface
The data order of the Serial Interface can select either MSB or LSB first by the mask option.
4)A/D Control Clock
A/D Control Clock can select either the external clock from ADCK terminal or the internal clock from the
prescaler by the mask option.
5)Each Internal Clock
The count clocks of Timer1 and Timer2, the Internal shift clock of the Serial Interface, the clock of the A/D
control clock and the output clock through the SCK/CKOUT terminal are clocks divided in the internal prescaler,
and the frequency of this clock can be selected by the mask option from follows which are dividing numbers
based on the inverse of the 1-instruction executing period (1/fOSC x 6).
1/2, 1/4, 1/8, 1/16, 1/32,1/64, 1/128, 1/256, 1/512, 1/1024, 1/2048,1/4096
Note) Count clock of Timer2 can select the internal or external clock by the program.
The shift clock of the serial interface can select the internal or external clock by the program.
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