NJU6678CL 查看數據表（PDF） - Japan Radio Corporation

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NJU6678CL

104-common x 132-segment BIT MAP LCD DRIVER

Japan Radio Corporation  

NJU6678

TERMINAL DESCRIPTION

No.

Symbol I/O

Function

1 to 8

DUMMY0

to

DUMMY7

Dummy Terminals.

These terminals are insulated.

9,46

VDD

Power VDD=+3V

13,30

VSS

GND VSS=0V

45

V1

Power LCD Driving Voltage Supplying Terminal. When the internal voltage booster is

44

V2

not used, supply each level of LCD driving voltage from outside with following

43

V3

relation.

42

V4

VDD>V1>V2>V3>V4>V5

41

V5

When the internal power supply is on, the internal circuits generate and supply

following LCD bias voltage from V1 to V4 terminals.

Bias

1/4Bias

1/5Bias

1/6Bias

1/7Bias

1/8Bias

1/9Bias

1/10Bias

1/11 Bias

V1

V2

V3

V4

V 5+ 3 / 4 V LCD V 5+ 2 / 4 V LCD V 5+ 2 / 4 VLCD V 5 + 1 / 4 VLCD

V 5+ 4 / 5 V LCD V 5+ 3 / 5 V LCD V 5+ 2 / 5 VLCD V 5 + 1 / 5 VLCD

V 5+ 5 / 6 V LCD V 5+ 4 / 6 V LCD V 5+ 2 / 6 VLCD V 5 + 1 / 6 VLCD

V 5+ 6 / 7 V LCD V 5+ 5 / 7 V LCD V 5+ 2 / 7 VLCD V 5 + 1 / 7 VLCD

V 5+ 7 / 8 V LCD V 5+ 6 / 8 V LCD V 5+ 2 / 8 VLCD V 5 + 1 / 8 VLCD

V 5+ 8 / 9 V LCD V 5+ 7 / 9 V LCD V 5+ 2 / 9 VLCD V 5 + 1 / 9 VLCD

V5+9/10V LCD V5+8/10V LCD V5 +2/10V LCD V5+1/10V LCD

V 5+10/11VLCD V 5+9/11V LCD V 5+2/11V LCD V5 +1/11V LCD

38,39

36,37

34,35

32,33

31

40

15

14

22 to 29

19

C1+,C1-

C2+,C2-

C3+,C3-

C4+,C4-

VOUT

VR

T1

T2

D0 to

D7

(SI)

(SCL)

A0

(VLCD=VDD-V5)

O Step up capacitor connecting terminals.

Voltage booster circuit (Maximum 5-time)

O Step up voltage output terminal. Connect the step up capacitor between this

terminal and VSS .

I Voltage adjust terminal. V5 level is adjusted by external bleeder resistance

connecting between VDD and V5 terminal.

I LCD bias voltage control terminals. ( *:Don't Care)

T1

T2

Voltage

booster Cir.

Voltage Adj.

V/F Cir.

L

*

Available

Available

Available

H

L

Not Avail.

Available

Available

H

H

Not Avail.

Not Avail.

Available

I/O P/S="H" : Tri-state bi-directional Data I/O terminal in 8-bit parallel operation.

P/S="L" : D7=Serial data input terminal. D 6=Serial data clock signal input

terminal.

Data from SI is loaded at the rising edge of SCL and latched as the

parallel

data at 8th rising edge of SCL.

I Connect to the Address bus of MPU. The data on the D 0 to D7 is

distinguished between Display data and Instruction by status of A0.

A0

Distin.

H

Display Data

L

Instruction

12

RES

I Reset terminal. When the RES terminal goes to "L", the initialization is

performed. Reset operation is executing during "L" state of RES.

18

CS

I Chip select terminal. Data Input/Output are available during CS ="L".

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