PA5750 查看數據表（PDF） - ProTek Devices.
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PA5750 Datasheet PDF : 30 Pages
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ANALOG PRODUCTS DIVISION
PA5750
Low Power Stereo Audio CODEC
With Speaker and Headphone Amplifier.
SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
P
S
START ADDRESS
R/W
ACK
DATA
ACK
DATA
Fig. 2 Complete DATA Transfer for 2-wire Interface
A master controller initiates the transmission by sending a “start” signal, which is defined as a high-to-low
transition at SDA while SCL is high. The first byte transferred is the slave address. It is a seven-bit chip address
followed by a R/W bit. The chip address must be 001000x where x = AD0 (pin CE). The R/W bit indicates the
slave DATA transfer direction.
Once an acknowledge bit is received, the DATA transfer starts to procede on a byte-by-byte basis in the
direction specified by the R/W bit. The master can terminate the communication by generating a “Stop” signal,
which is defined as a low-to-high transition at SDA while SCL is high.
In 2-wire interface mode, the registers can be written to and read. The format of “write” and “Read” instructions
are shown in Tables 3 and 4. To Read DATA from a register R/W must be set to “0” to access the register
address and then set to “1” to read DATA in the register. There is NO acknowledge bit after data to be written
or read, this is the only difference from the I2C protocol.
Table 3 Write DATA to register in 2-wire Interface Mode
Chip Address
00100
AD0
R/W
0
ACK
Register Address
RAM
DATA to be written
ACK
DATA
Chip Address
001000
Chip Address
001000
Table 4 Read DATA from Register in 2-wire Interface Mode
R/W
Register Address
AD0
0
ACK
RAM
R/W
DATA to be Read
AD0
1
ACK
DATA
6. CONFIGURATION REGISTER DEFINITION
SPI and 2-wire configuration interface share the same registers because there is only one interface active at any
given time. There are a total of 53 user programmable 8-bit registers in the PA5750. These registers control the
operations of ADC and DAC. External master controller can access these registers by using the slave address
specified in RAM (Register Address Map) register as shown in Table 5.
Table 5. Bit Content of Register Address Map (RAM)
Reg. 00
Reg. 01
Reg. 02
Reg. 03
Reg. 04
Reg. 05
Reg. 06
Reg. 07
B7
SCPReset
TSDN
adc_DigPDN
Pdn_AINL
Pdn_DACL
LPDACL
LPPGA
B6
LRCM
Pdn_OC
dac_DigPDN
Pdn_AINR
Pdn_DACR
LPDACR
LPLMIX
B5
DACMCLK
LPVcmMod
adc_stm_rst
Pdn_ADCL
LOUT1
LPLOUT1
LPRMIX
B4
SameFs
LPVrefBuf
dac_stm_rst
Pdn_ADCR
ROUT1
LPROUT1
LPMMIX
B3
SeqEn
Pdn_Ana
ADCDLL_PDN
Pdn_MICB
LOUT2
LPLOUT2
LPMOUTINV
VSEL
B2
EnRef
Pdn_lbiasgen
DACDLL_PDN
Pdn_ADCBiasgen
ROUT2
LPROUT2
LPOUT2INV
B1
B0
VMIDSEL
Vrefr_Lo
Pdn_Vrefbuf
adcVref_PDN
flashLP
dacVref_PDN
int1LP
MONO
OUT3
LPMONO
LPADCvrp
LPOUT3
LPDACvrp
561 E Elliot Road.#175 Chandler, AZ 85225 Tel: (480)539-2900. Fax: (480)632-1715.
8
95230 Rev.0. 04/09
www.protekanalog.com
Not for use in any life support systems.
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