ST63E73 查看數據表（PDF） - STMicroelectronics

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ST63E73

8-BIT ROM/OTP/EPROM MCUs FOR DIGITALLY CONTROLLED MULTISYNC/MULTISTANDARD MONITORS

STMicroelectronics 

ST6373

MEMORY SPACES (Cont’d)

1.3.3 Data Space

The ST6 Core instruction set operates on a specif-

ic space, referred to as the Data Space, which

contains all the data necessary for the program.

The Data Space allows the addressing of RAM

(192 bytes), EEPROM (384 bytes plus 128 bytes

for the DDC SPI), ST6 Core and peripheral regis-

ters, as well as read-only data such as constants

and look-up tables.

Figure 5. Data Space

DATA RAM/EEP ROM

BANK AREA

DATA ROM

WIND OW AREA

X REGISTER

Y REGISTER

V REGISTER

W REGISTER

DATA RAM

PORT A DATA REGISTER

PORT B DATA REGISTER

PORT C DATA REGISTE R

RESERVED

PORT A DIRECT ION REGISTE R

PORT B DIRECT ION REGISTE R

PORT C DIRECTION REGISTER

RESERVED

INTERRUPT OPTION REGISTER

DATA ROM WINDO W REGISTE R

PROGRAM ROM PAGE REGISTER

I C SPI DATA REGISTER

DDC SPI DATA REGISTE R

PORT A OPTION REGISTER

PORT B OPTION REGISTER

RESERVED

ADC RESULT REGISTER

ADC CONTROL REGISTER

TIMER 1 PRESC ALER REGISTER

TIMER 1 COUNTER REGISTE R

TIMER 1 STATUS /CONTROL REGISTER

TIMER 2 PRESC ALER REGISTER

TIMER 2 COUNTER REGISTE R

WATCHD OG REGISTER

000h

03Fh

040h

07Fh

080h

081h

082h

083h

084h

0BFh

0C0h

0C1h

0C2h

0C3h

0C4h

0C5h

0C6h

0C7h

0C8h

0C9h

0CAh*)

0CBh

0CCh

0CDh

0CEh

0CFh

0D0h

0D1h*)

0D2h

0D3h

0D4h

0D5h

0D7h

0D8h

MIRROR REGISTER

TIMER 3 PRESCALER REGISTER

TIMER 3 COUNTER REGISTER

TIMER 3 STAT US/CONTROL REGISTER

EVENT COUNTER DATA REGISTER 1

EVENT COUNTER DATA REGISTER 2

SYNC PROCESSOR CONTROL REGISTE R

D/A 0/4 DATA CONTROL REGISTER

D/A 1/5 DATA CONTROL REGISTER

D/A 2/6 DATA CONTROL REGISTER

D/A 3/7 DATA CONTROL REGISTER

D/A 8 DATA CONTROL REGISTER

I C SPI CONTROL REGISTE R 1

I C SPI CONTROL REGISTE R 2

D/A BANK REGISTER

DATA RAM BANK REGISTER

DDC EEPROM CONTROL REGISTER

EEPROM CONTROL REGISTER

DDC SPI CONTROL REGISTER 1

DDC SPI CONTROL REGISTER 2

NMI/PWRI N/VSYNC INTERRU PT REGIST ER

HDA DATA REGISTER 1

HDA DATA REGISTER 2

PERIOD COUNTER DATA REGISTER

PERIOD COUNTER 1 AND BLANK CTRL REG.

AUTO-COU NTER REGISTER

SCL LATCH AND DDC2B ADDRESS CTRL REG.

XOR REGIST ER

RESERVE D

ACCUMULATOR

0D9h

0DAh

0DBh

0DCh

0DDh

0DEh*)

0DFh*)

0E0h*)

0E1h*)

0E2h*)

0E3h*)

0E4h*)

0E5h*)

0E6h*)

0E7h

0E8h

0E9h

0EAh

0EBh

0ECh

0EDh

0EEh*)

0EFh*)

0F0h

0F1h*)

0F2h

0F3h*)

0F4h

0F5h

0FEh

0FFh

*) These registers contain write only bits, in which

case the bit operation instructions are not possi-

ble.

10/64

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