PDI1394L21 查看數據表（PDF） - Philips Electronics
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PDI1394L21 Datasheet PDF : 52 Pages
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Philips Semiconductors
1394 full duplex AV link layer controller
Preliminary specification
PDI1394L21
8.0 APPLICATION DIAGRAM
MPEG OR DVC
DECODER
AV
INTERFACE
MPEG OR DVC
DECODER
AV
INTERFACE
PDI1394L21
AV LINK
DATA 8/
ADDRESS 9/
INTERRUPT & CONTROL
PHY–LINK
INTERFACE
PDI1394Pxx
PHY
1394 CABLE
INTERFACE
HOST CONTROLLER
SV00880
9.0 PIN DESCRIPTION
9.1 Host Interface
PIN No.
PIN SYMBOL I/O
NAME AND FUNCTION
1, 2, 3, 4, 7, 8,
9, 10
HIF D[7:0]
I/O Host Interface Data 7 (MSB) through 0. Byte wide data path to internal registers.
5, 12, 23, 31,
38, 44, 50, 63,
73, 79, 87, 93
GND
Ground reference
6, 13, 24, 32,
39, 45, 49, 64,
VDD
72, 78, 88, 94
3.3V ± 0.3V power supply
14, 15, 16, 17,
18, 19, 20, 21,
22
HIF A[8:0]
I
Host Interface Address 0 through 8. Provides the host with a byte wide interface to internal
registers. See description of Host Interface for addressing rules.
25
HIF CS_N
I
Chip Select (active LOW). Host bus control signal to enable access to the FIFO and control and
status registers.
Write enable. When asserted (LOW) in conjunction with HIF CS_N, a write to the PDI1394L21
internal registers is requested. (NOTE: HIF WR_N and HIF RD_N : if these are both LOW in
26
HIF WR_N
I conjunction with HIF CS_N, then a write cycle takes place. This can be used to connect CPUs
that use R/W_N line rather than separate RD_N and WR_N lines. In that case, connect the
R/W_N line to the HIF WR_N and tie HIF RD_N LOW.)
27
HIF RD_N
I
Read enable. When asserted (LOW) in conjunction with HIF CS_N, a read of the PDI1394L21
internal registers is requested.
28
HIF INT_N
O
Interrupt (active LOW). Indicates a interrupt internal to the PDI1394L21. Read the General
Interrupt Register for more information. This pin is open drain and requires a 1KW pull-up resistor.
29
RESET_N
I Reset (active LOW). The asynchronous master reset to the PDI1394L21.
1999 Aug 06
5
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