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LC866428A 查看數據表(PDF) - SANYO -> Panasonic

零件编号
产品描述 (功能)
比赛名单
LC866428A
SANYO
SANYO -> Panasonic SANYO
LC866428A Datasheet PDF : 22 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LC866432A/28A/24A/20A/16A/12A/08A
(14) Subroutine stack levels
- 128 levels (Max.) : Stack area included in RAM area
(15) Multiplication and division
16-bit ! 8-bit (7 instruction cycle times)
16-bit / 8-bit (7 instruction cycle times)
(16) Three oscillation circuits
- On-chip RC oscillation circuit using for the system clock.
- On-chip CF oscillation circuit using for the system clock.
- On-chip crystal oscillation circuit using for the system clock and for time-base clock.
(17) Standby function
- HALT mode function
The HALT mode is used to reduce power dissipation. In this operation mode, program execution is stopped.
This operation mode can be released by interrupt request signals or the initial system reset request signal.
- HOLD mode function
The HOLD mode is used to freeze all the oscillations ;
RC (internal), CF and Crystal oscillations. This mode can be released by the following operations
• Reset terminal (RES) set to Low level
• Input a assigned level to P70 / INT0 / T0IN or P71 / INT1 / T0IN terminal
• Input a Port 0 interrupt condition
(18) Factory shipment
• QIP80E delivery form
(19) Development support tools
Evaluation (EVA) chip : LC866097
EPROM version
: LC86E6448
One time version
: LC86P6448
Emulator
: EVA-86000 + ECB866400 (Evaluation chip board) + POD866400 (POD)
• Notes for use
1. Set VDD=4.0V to 6.0V at using S16 to S37 as input port.
2. Follow the under table.
Frequency range
of the system clock
15kHz to 30kHz
30kHz to 6MHz
15kHz to 30kHz
30kHz to 1.5MHz
1.5MHz to 3MHz
Internal RC oscillation
Voltage range
4.5V to 6.0V
2.5V to 6.0V
4.5V to 6.0V
2.5V to 6.0V
Clock
Divider
1/1
1 / 1, 1 / 2
1/1
1 / 1, 1 / 2
1/2
1 / 1, 1 / 2
1/2
Note
Can not use 1 / 2 divider
Can not use 1 / 2 divider
Can not use 1 / 1 divider
Can not use 1 / 1 divider
No.6739-4/22

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