PMB2304 查看數據表（PDF） - Infineon Technologies

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PMB2304

Wireless Components PLL-Frequency Synthesizer

Infineon Technologies 

PMB 2304R

preliminary

Functional Description

14 MFO1

15 MFO2

16 LD

pin 14

2pF

MFO1

ESD

560Ω

IREF

VREF

Internal Charge

Pump Mode

& standby

VREF

MF02

2pF Pin15

ESD

pin 16

2pF

LD

ESD

Multifunction Output for the signals fRN ,

ΦV,, ΦVN , and port1.

–The signal fRN is the divided signal of the

reference frequency.

The L-time corresponds to 1/fRI respec-

tively

–In the port function the port 1 output sig-

nal is assigned to the information of the

programmed status. The output switches

with the rising edge of the EN-signal

The standby mode does not affect the

port function.

Multifunction I/O-Pin for the external ref-

erence current setting IREF and the signals

ΦRN and fVN ( in testmode).

–The signal fVN is the divided signal of FI-

input. The L-time corresponds to 1/fFI

respectively.

Output levels are not specified, the signal

should only be used for test purpose.

–In the internal charge pump mode the

reference current IREF at MFO2 deter-

mines the value of the PD-output current.

Lock Detector Output (open drain). Uni-

polar output of the phase detector in the

form of a pulse-width modulated signal.

The LD-pulse width corresponds to the

phase difference. In the locked state the

LD-signal is at H-level. For standby mode

see Standby Table.

Only for ABL status 11 no gating of ABL

impulse is performed.

Wireless Components

3-5

Specification, June 2002

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