R5F212C7SDFP 查看數據表（PDF） - Renesas Electronics

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R5F212C7SDFP

RENESAS MCU

Renesas Electronics 

R8C/2C Group, R8C/2D Group

2. Central Processing Unit (CPU)

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a

register bank. There are two sets of register bank.

b31

R2

R3

b15

b8b7

b0

R0H (high-order of R0) R0L (low-order of R0)

R1H (high-order of R1) R1L (low-order of R1)

R2

R3

A0

A1

FB

Data registers(1)

Address registers(1)

Frame base register(1)

b19

b15

b0

INTBH

INTBL

The 4 high order bits of INTB are INTBH and

the 16 low order bits of INTB are INTBL.

b19

b0

PC

Interrupt table register

Program counter

b15

b0

USP

ISP

SB

b15

b0

FLG

b15

IPL

b8 b7

b0

U I OB S ZDC

NOTE:

1. These registers comprise a register bank. There are two register banks.

Figure 2.1 CPU Registers

User stack pointer

Interrupt stack pointer

Static base register

Flag register

Carry flag

Debug flag

Zero flag

Sign flag

Register bank select flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved bit

Processor interrupt priority level

Reserved bit

Rev.1.00 Feb 09, 2007 Page 14 of 55

REJ03B0183-0100

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