RTL8130 查看數據表（PDF） - Realtek Semiconductor
零件编号
产品描述 (功能)
比赛名单
RTL8130 Datasheet PDF : 55 Pages
| |||
RTL8130 Preliminary
operation is complete.
3
R/W
RE
Receiver Enable
2
R/W
TE
Transmitter Enable
1
-
-
Reserved
0
R
BUFE
Buffer Empty: Rx Buffer Empty. There is no packet stored in the Rx
buffer ring.
5.5 Interrupt Mask Register (Offset 003Ch-003Dh, R/W)
Bit
R/W
Symbol
Description
15
R/W
SERR
System Error Interrupt: 1 => Enable, 0 => Disable.
14
R/W
TimeOut
Time Out Interrupt: 1 => Enable, 0 => Disable.
13
R/W
LenChg
Cable Length Change Interrupt: 1 => Enable, 0 => Disable.
12-7
-
-
Reserved
6
R/W
FOVW
Rx FIFO Overflow Interrupt: 1 => Enable, 0 => Disable.
5
R/W
PUN/LinkChg Packet Underrun/Link Change Interrupt: 1 => Enable, 0 => Disable.
4
R/W
RXOVW
Rx Buffer Overflow Interrupt: 1 => Enable, 0 => Disable.
3
R/W
TER
Transmit Error Interrupt: 1 => Enable, 0 => Disable.
2
R/W
TOK
Transmit OK Interrupt: 1 => Enable, 0 => Disable.
1
R/W
RER
Receive Error Interrupt: 1 => Enable, 0 => Disable.
0
R/W
ROK
Receive OK Interrupt: 1 => Enable, 0 => Disable.
5.6 Interrupt Status Register (Offset 003Eh-003Fh, R/W)
Bit
15
14
13
12 - 7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Symbol
SERR
TimeOut
LenChg
-
FOVW
PUN/LinkChg
RXOVW
TER
TOK
RER
ROK
Description
System Error: Set to 1 when the RTL8130 signals a system error on
the PCI bus.
Time Out: Set to 1 when the TCTR register reaches to the value of the
TimerInt register.
Cable Length Change: Cable length is changed after Receiver is
enabled.
Reserved
Rx FIFO Overflow
Packet Underrun/Link Change: Set to 1 when CAPR is written but Rx
buffer is empty, or when link status is changed.
Rx Buffer Overflow: Set when receive (Rx) buffer ring storage
resources have been exhausted.
Transmit (Tx) Error: Indicates that a packet transmission was
aborted, due to excessive collisions, according to the TXRR's setting
Transmit (Tx) OK: Indicates that a packet transmission is completed
successfully.
Receive (Rx) Error: Indicates that a packet has either CRC error or
frame alignment error (FAE). The collided frame will not be
recognized as CRC error if the length of this frame is shorter than 16
byte.
Receive (Rx) OK: In normal mode, indicates the successful
completion of a packet reception. In early mode, indicates that the Rx
byte count of the arriving packet exceeds the early Rx threshold.
1999/5/30
13
Ver.1.1
Share Link: 