RTL8130 查看數據表（PDF） - Realtek Semiconductor
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RTL8130 Datasheet PDF : 55 Pages
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RTL8130 Preliminary
5.7 Transmit Configuration Register (Offset 0040h-0043h, R/W)
Bit
31
30-28
27
26
25-24
23-19
18, 17
16
15-11
10-8
7-4
3-1
0
R/W
-
R
R
R
R/W
-
R/W
R/W
-
R/W
R/W
-
W
Symbol
-
HWVER
OEMID
8130ID
IFG1, 0
-
LBK1, LBK0
CRC
-
MXDMA2, 1, 0
TXRR
-
CLRABT
Description
Reserved
Hardware Version number: 7 for RTL8139A and RTL8130
6 for RTL8139
OEM ID = 1
RTL8130ID = 1
Interframe Gap Time: This field allows the user to adjust the
interframe gap time below the standard: 9.6 us for 10Mbps, 960 ns for
100Mbps. The time can be programmed from 9.6 us to 8.4 us
(10Mbps) and 960ns to 840ns (100Mbps). Note that any value other
than zero will violate the IEEE 802.3 standard.
The formula for the inter frame gap is:
10Mbps
8.4us + 0.4(IFG(1:0)) us
100Mbps
840ns + 40(IFG(1:0)) ns
Reserved
Loopback test. There will be no packet on the TX+/- lines under the
Loopback test condition. The loopback function must be independent
of the link state.
00 : normal operation
01 : MAC Loopback
10 : PHY Loopback
11 : Twister Loopback
Append CRC: Setting to 1 means that there's no CRC appended at the
end of a packet. Setting to 0 means that there's CRC appended at the
end of a packet.
Reserved
Max DMA Burst Size per Tx DMA Burst: This field sets the
maximum size of transmit DMA data bursts according to the
following table:
000 = 16 bytes
001 = 32 bytes
010 = 64 bytes
011 = 128 bytes
100 = 256 bytes
101 = 512 bytes
110 = 1024 bytes
111 = 2048 bytes
Tx Retry Count: These are used to specify additional transmission
retries in multiple of 16(IEEE 802.3 CSMA/CD retry count). If the
TXRR is set to 0, the transmitter will re-transmit 16 times before
aborting due to excessive collisions. If the TXRR is set to a value
greater than 0, the transmitter will re-transmit a number of times
equals to the following formula before aborting:
Total retries = 16 + (TXRR * 16)
The TER bit in the ISR register or transmit descriptor will be set
when the transmission fails and reaches to this specified retry count.
Reserved
Clear Abort: Setting this bit to 1 causes the RTL8130 to retransmit
the packet at the last transmitted descriptor when this transmission
was aborted, Setting this bit is only permitted in the transmit abort
state.
1999/5/30
14
Ver.1.1
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