SAA2520 查看數據表（PDF） - Philips Electronics

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SAA2520

Stereo filter and codec for MPEG layer 1 audio applications

Philips Electronics 

Philips Semiconductors

Stereo filter and codec for MPEG layer 1

audio applications

Preliminary specification

SAA2520

channel

SWS

L R L RL R LR LR LR LR

FSYNC

sub-band

31

0

1

31

0

1

MBC148 - 1

Fig.10 SWS related to phase of FSYNC.

Baseband Interface Signals

The interface between the SAA2520 and the baseband input/output circuitry consists of the following signals:

SWS

bi-directional

word (channel) select

FS

SCL

bi-directional

bit clock

64FS

SDA

bi-directional

baseband data

FDIR

output

decoding mode (direction control)

The SWS signal indicates the channel of the sample signal

(either LEFT or RIGHT) and is equal to the sampling

frequency FS.

Operating at a frequency of 64 times that is used for

sampling, the bit clock dictates that each SWS period

contains 64 SDA data bits. Of these, a maximum of 36 are

used to transfer data (samples may have a length up to

18-bits). Samples are transferred most significant bit first.

Both SWS and SDA change state at the negative edge of

SCL.

This baseband data is transferred between the SAA2520

and the input/output using either Standard I2S (default) or

the alternative format shown in Fig.8.

August 1993

10

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