SAA2520 查看數據表（PDF） - Philips Electronics

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产品描述 (功能)

比赛名单

SAA2520

Stereo filter and codec for MPEG layer 1 audio applications

Philips Electronics 

Philips Semiconductors

Stereo filter and codec for MPEG layer 1

audio applications

Preliminary specification

SAA2520

PINNING

SYMBOL

FS256

MUTEDAC

DEEMDAC

ATTDAC

VSS

URDA

SBDIR

SBDA

SBCL

SBWS

SBEF

SBMCLK

SYNCDAI

FDIR

FRESET

FSYNC

FDAF

FDAC

SCL

SWS

SDA

PWRDWN

DSC4

DSC3

DSC2

DSC1

DSC0

VDD

RESET

T1

T0

LTDATA

LTCLK

PIN

DESCRIPTION

TYPE

1 (Filtered)-I2S clock; 256 × sample frequency. 12 mA 3-state output + CMOS

I/O

input with pull-down

2 DAC control/output expander

O

3 DAC control/output expander

O

4 DAC control/output expander

O

5 supply ground (0 V)

6 unreliable drive processing data; CMOS level

I

7 sub-band I2S direction: (SWBS, SBCL, SBDA); CMOS level

I

8 sub-band I2S data; 4 mA, 3-state output + CMOS input with pull-down

I/O

9 sub-band I2S bit clock; 4 mA, 3-state output + CMOS input with pull-down

I/O

10 sub-band I2S word select; 4 mA, 3-state output + CMOS input with pull-down

I/O

11 sub-band I2S byte error flag; CMOS level

I

12 sub-band I2S clock, 6.144 MHz locked to FS256; 8 mA, 3-state output + CMOS O

input with pull-down

13 DAI synchronization pulse

O

14 (Filtered)-I2S direction: (FDAC, FDAF, SDA);

O

15 reset signal for SAA2521

O

16 Filtered-I2S sync signal for SAA2521

O

17 Filtered-I2S sub-band filter data; 4 mA, 3-state output + CMOS input with

I/O

pull-down

18 Filtered-I2S sub-band codec data; 4 mA, 3-state output + CMOS input with

I/O

pull-down

19 I2S bit clock; 4 mA, 3-state output + CMOS input with pull-down

I/O

20 I2S-word select; 4 mA, 3-state output + CMOS input with pull-down

I/O

21 I2S baseband data filter; 4 mA, 3-state output + CMOS input with pull-down

I/O

22 power-down mode; CMOS level

I

23 test pin

24 test pin

25 test pin

26 test pin

27 test pin

28 positive supply voltage (+5 V)

29 system reset; CMOS level with pull-down and hysteresis

I

30 test pin; do not connect

31 test pin; do not connect

32 LT interface data; 4 mA, 3-state output + CMOS input with pull-down

I/O

33 LT interface bit clock; CMOS level

I

August 1993

4

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