SAA7167 查看數據表（PDF） - Philips Electronics
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SAA7167 Datasheet PDF : 20 Pages
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Philips Semiconductors
YUV-to-RGB Digital-to-Analog
Converter (DAC)
Preliminary specification
SAA7167
Voltage output amplifiers
Before the analog input enters the analog mixers, it passes
through voltage output amplifiers. Level shifters are used
internally to provide an offset of 0.2 V and an amplifier gain
of 2 for analog inputs to match with the output levels from
DACs. After buffering with voltage output amplifiers, the
final RGB outputs can drive a 150 Ω load directly (25 Ω
internal resistor, 50 Ω external serial resistor, and 75 Ω
load resistor at monitor side (see Fig.9).
The output voltage level of DAC ranges from the lowest
level 0.2 V (zero code) to the highest level 1.82 V (all one
code).
With the digital input YUV video data in accordance with
CCIR-601, the RGB output of 8-bit DAC actually ranges
from the 16th step (black) to the 235th step (white).
Therefore, after the voltage divider with external serial
resistor and monitor load resistor, the output voltage range
to monitor is approximately 0.7 V (peak-to-peak).
I2C-bus control
Only one control byte is needed for the SAA7167.
The I2C-bus format is shown in Table 6.
Table 6 I2C-bus format
S
slave address
A
subaddress
A
data
A
P
Notes
1. S = START condition.
2. Slave address = 1011 111X; this slave address is identical to the one for the SAA9065; X = R/W control bit:
a) X = 0; order to write.
b) X = 1; order to read (not used for SAA7167).
3. A = acknowledge; generated by the slave.
4. Subaddress = subaddress byte.
5. Data = data byte.
6. P = STOP condition.
Table 7 Control data byte
SUBADDRESS
00
01
02
D7
KMOD2
0
KD7
D6
KMOD1
0
KD6
D5
KMOD0
0
KD5
D4
DRP
0
KD4
D3
KEN
0
KD3
D2
KINV
KDLY2
KD2
D1
FMTC1
KDLY1
KD1
D0
FMTC0
KDLY0
KD0
1995 Nov 03
8
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