XC886/888CLM
Electrical Parameters
VDDP
VPAD
VDDC
OSC
tOSCST
PLL
PLL unlock
PLL lock
tLOCK
Flash State
tRST
RESET
Reset
Initialization
tFINIT
Ready to Read
Pads
2)
1)
3)
1)Pad state undefined 2)ENPS control 3)As Programmed
I)until EVR is stable II)until PLL is locked III) until Flash go IV) CPU reset is released; Boot
to Ready-to-Read ROM software begin execution
Figure 4-1 Power-on Reset Timing
Data Sheet
Prelimary
107
V0.1, 2006-02