SAF-XC888-8FFI 查看數據表（PDF） - Infineon Technologies

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SAF-XC888-8FFI

8-Bit Single-Chip Microcontroller

Infineon Technologies 

XC886/888CLM

4.3.6 SSC Master Mode Timing

Electrical Parameters

Table 47

SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF)

Parameter

Symbol

Limit Values

min.

max.

SCLK clock period

t0 CC 2*TSSC 1) –

MTSR delay from SCLK

t1 CC 0

tbd

MRST setup to SCLK

t2 SR tbd

–

MRST hold from SCLK

t3 SR tbd

–

1) TSSCmin = TCPU = 1/fCPU. When fCPU = 24MHz, t0 = 83.3ns. TCPU is the CPU clock period.

Unit

ns

ns

ns

ns

t0

SCLK1)

t1

t1

MTSR1)

t2

t3

MRST1)

Data

valid

t1

1) This timing is based on the following setup: CON.PH = CON.PO = 0.

SSC_Tmg1

Figure 46 SSC Master Mode Timing

Data Sheet

Prelimary

111

V0.1, 2006-02

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