SAKC505A-2R 查看數據表（PDF） - Infineon Technologies

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SAKC505A-2R

8-Bit Single-Chip Microcontroller

Infineon Technologies 

C505/C505C/C505A/C505CA

Table 2

Pin Definitions and Functions (cont’d)

Symbol

EA

Pin Number I/O

*)

29

I

P0.0-P0.7 37-30

I/O

VAREF

38

–

VAGND

39

–

VSS

16

–

VDD

17

–

*) I = Input

O = Output

Function

External Access Enable

When held at high level, instructions are fetched from the

internal program memory when the PC is less than 4000H

(C505(C)(A)-2R) or 8000H (C505A-4R/C505CA-4R/C505A-

4E/C505CA-4E). When held at low level, the C505 fetches

all instructions from external program memory.

For the C505 romless versions (i.e. C505-L, C505C-L,

C505A-L and C505CA-L) this pin must be tied low.

For the ROM protection version EA pin is latched during

reset.

Port 0

is an 8-bit open-drain bidirectional I/O port. Port 0 pins that

have 1’s written to them float, and in that state can be used

as high-impendance inputs. Port 0 is also the multiplexed

low-order address and data bus during accesses to external

program or data memory. In this application it uses strong

internal pullup transistors when issuing 1’s.

Port 0 also outputs the code bytes during program

verification in the C505 ROM versions. External pullup

resistors are required during program verification.

Reference voltage for the A/D converter.

Reference ground for the A/D converter.

Ground (0V)

Power Supply (+5V)

Data Sheet

10

12.00

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