SAKC505A-2R 查看數據表（PDF） - Infineon Technologies

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SAKC505A-2R

8-Bit Single-Chip Microcontroller

Infineon Technologies 

C505/C505C/C505A/C505CA

CAN Controller Software Initialization

The very first step of the initialization is the CAN controller input clock selection. A divide-by-2

prescaler is enabled by default after reset (Figure 16). Setting bit CMOD (SYSCON.3) disables the

prescaler. The purpose of the prescaler selection is:

– to ensure that the CAN controller is operable when fosc is over 10 MHz (bit CMOD =0)

– to achieve the maximum CAN baudrate of 1 Mbaud when fosc is 8 MHz (bit CMOD=1)

SYSCON.3

(CMOD)

f OSC

1

2

0

f CAN

Full-CAN

Module

Condition: CMOD = 0, when f OSC > 10 MHz

MCS03296

Frequency (MHz) CMOD

BRP

CAN

fOSC

fCAN

(SYSCON.3) (BTR0.0-5) baudrate

(Mbaud/sec)

8

8

8

4

16

8

1

000000B

1

0

000000B

0.5

0

000000B

1

Note : The switch configuration shows the reset state of bit CMOD.

Figure 16

CAN controller Input Clock Selection

Data Sheet

37

12.00

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