SC420A 查看數據表（PDF） - Semtech Corporation

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SC420A

High Speed, Combi-Sense™, Synchronous Power MOSFET Driver for Mobile Applications

Semtech Corporation 

SC420A

POWER MANAGEMENT

Applications Information

Combi-Sense (Lossless current sense)

input supply and ground, a shoot-through condition dur-

Combi-Sense is a method to sense the output current

on a combination of power devices. There is no sense

resistor and the current is sensed on: Top MOSFET, bot-

tom MOSFET and output inductor.

ing which both the top and bottom FET’s could be on

momentarily. The top FET is also prevented from turn-

ing on until the bottom FET is off. The top FET turn-on

delay is internally set to 30ns (typical) and may be

programmably extended by an external capacitor on the

Cdelay pin, the delay is increased by 1ns/pf.

An internal phase node VPN sends a signal which is inte-

grated by the Combi-Sense network. This network con-

sists of a resistor and capacitor in series, connected

between VPN and the DRN pins. The resulting signal is

large, clean and not duty cycle sensitive. It can be used

The EN (enable) pin may be used to turn both TG and BG

drives off. This lowers power consumption by reducing

the quiescent current draw of the SC420A to IQsd.

directly for close loop current mode control and current CO Undriven

limit.

Fast Switching Drives

If the CO pin is undriven it will be pulled to GND by an

internal pull down resistor. This will switch the BG pin

high and the TG pin low.

As the switching frequency of PWM controllers is increased

to reduce power supply volume and cost, fast rise and Over Temperature Shutdown

fall times are necessary to minimize switching losses (TOP

MOSFET) and reduce dead-time (BOTTOM MOSFET) The SC420A will shutdown by pulling both driver’s low if

losses. While low Rds_On MOSFET’s present a power

saving, the MOSFETs die area is larger and the effective

input capacitance of the MOSFET is increased. Often a

its junction temperature, TJ, exceeds 165°C. The driv-

ers will resume operation when TJ declines below 155oC.

50% decrease in Rds_On doubles the effective input Supply Voltage

gate charge, which must be supplied by the driver. The

Rds_On power savings can be offset by the switching

and dead-time losses with a suboptimum driver. While

discrete solution can achieve reasonable drive capabil-

ity, implementing shoot-through, programmable delay and

other housekeeping functions necessary for safe opera-

tion can become cumbersome and costly. The SC420A

presents a total solution for the high-speed, high power

density applications. Wide input supply range of 4.5V-

25V allows use in battery powered applications, new high

voltage, distributed power supplies.

The SC420A can operate from 4.75V to 6V. The VIN pin

bypass capacitor must also be less than 0.5in away from

the SC420A. The ground node of this capacitor, the

SC420A PGND pin and the Source of the bottom FET

must be very close to each other, preferably with com-

mon PCB copper land with multiple vias to the ground

plane (if used). The parallel Schottky (if used) must be

physically next to the Bottom FET’s drain and source pins.

Any trace or lead inductance in these connections will drive

current away from the Schottky and allow it to flow through

Shoot Through Protection

the FET’s Body diode, thus reducing efficiency.

The control input (CO) to the SC420A is typically supplied

by a PWM controller that regulates the power supply out-

put. The timing diagram demonstrates the sequence of

events by which the top and bottom drive signals are

applied. The shoot-through protection is implemented

by holding the bottom FET off until the voltage at the

phase node (intersection of top FET source, the output

inductor and the bottom FET drain) has dropped below

1V. This assures that the top FET has turned off and

that a direct current path does not exist between the

Preventing Inadvertent Bottom Gate Turn-on

At high VIN2 input voltages, (12V and greater) a fast turn-

on of the top FET creates a positive going spike on the

Bottom FET’s gate through the Miller capacitance, Crss of

the bottom FET. The voltage appearing on the gate due to

this spike is:

VSPIKE

=

Vin * Crss

(Crss + Ciss )

© 2004 Semtech Corp.

8

United States Patent No. 6,441,597

www.semtech.com

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