SC420A 查看數據表（PDF） - Semtech Corporation

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SC420A

High Speed, Combi-Sense™, Synchronous Power MOSFET Driver for Mobile Applications

Semtech Corporation 

SC420A

POWER MANAGEMENT

Applications Information (Cont.)

Where Ciss is the input gate capacitance of the bottom

FET. This is assuming that the impedance of the drive

path is too high compared to the instantaneous imped-

ance of the capacitors, since dV/dT and thus the effective

frequency is very high. If the BG pin of the SC420A is very

close to the bottom FET, Vspike will be reduced depending

on trace inductance, rate of rise of current, etc.

A capacitor may be added from the gate of the Bottom

FET to its source, preferably less than 0.5in away. This

capacitor will be added to Ciss in the above equation to

reduce the effective spike voltage.

far negative, thus causing improper operation, double puls-

ing or at worst driver damage. On the SC420A, the drain

node, DRN, can go as far as 2V below ground without

affecting operation or sustaining damage.

The ringing is also an EMI nuisance due to its high reso-

nant frequency. Adding a capacitor, typically 1000-

2000pf, in parallel with Coss of the bottom FET will of-

ten eliminate the EMI issue.

Prevent Driver Overvoltage

The bottom MOSFET must be selected with attention

paid to the Crss/Ciss ratio. A low ratio reduces the Miller

feedback and thus reduces Vspike. Also MOSFETs with

higher Turn-on threshold voltages will conduct at a higher

voltage and will not turn on during the spike. A zero ohm

bottom FET gate resistor will obviously help keeping the

gate voltage low during off time.

Ultimately, slowing down the top FET by adding boost re-

sistance will reduce di/dt which will in turn make the effec-

tive impedance of the capacitors higher, thus allowing the

BG driver to hold the bottom gate voltage low. It does this

at the expense of increased switching times (and switch-

ing losses) for the top FET.

The top MOSFET source must be close to the bottom

MOSFET drain to prevent ringing and the possibility of

the phase node going negative. This frequency is deter-

mined by:

The negative voltage spikes on the phase node adds to

the bootstrap capacitor voltage, thus increasing the volt-

age between VBST - VDRN. This is of special importance

if higher boost voltages are used. If the phase node

negative spikes are too large, the voltage on the boost

capacitor could exceed device’s absolute maximum rat-

ing of 7V. To eliminate the effect of the ringing on the

boost capacitor voltage, place a 1 - 10 Ohm resistor be-

tween boost Schottky diode and VIN to filter the negative

spikes on DRN Pin. Initially populate it by 0 ohm. Alter-

nately, a Silicon diode, such as the commonly available

1N4148 can substitute for the Schottky diode and elimi-

nate the need for the series resistor.

Proper layout will guarantee minimum ringing and elimi-

nate the need for external components. Use of surface

mount MOSFETs, while increasing thermal resistance,

will reduce lead inductance as well as radiated EMI.

Fring

=

1

(2Π * Sqrt (LST

*Coss )

=

2π

1

LST * COSS

-Where:

LST = The effective stray inductance of the top FET added to

trace inductance of the connection between top FET’s source

and the bottom FET’s ground connection.

COSS = Drain to Source capacitance of the bottom FET. If

there is a Schottky used, the capacitance of the Schottky is

added to this value

Although this ringing does not pose any power losses due

to a fairly high Q, it could cause the phase node to go too

© 2004 Semtech Corp.

9

United States Patent No. 6,441,597

www.semtech.com

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