SII141 查看數據表（PDF） - Unspecified

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SII141

SiI 141B PanelLink® Digital Receiver

Unspecified 

Timing Diagrams

SiI 141B

SiI-DS-0037-C

SiI141B

2.0 V

2.0 V

2.0 V

10pF (5pF)

0.8 V

DLHT

Figure 1. Digital Output Transition Times

0.8 V

DHLT

RCIH

RCIP

2.0 V

2.0 V

0.8 V

0.8 V

RCIL

Figure 2. Receiver Clock Cycle/High/Low Times

RX0

RX1

RX2

Output Timing

VDIFF = 0V

TCCS

VDIFF = 0V

Figure 3. Channel-to-Channel Skew Timing

ODCK_INV = 1

ODCK_INV = 0

QE[23:0]/QO[23:0],

DE, VSYNC, HSYNC,

CTL[3:1]

TSETUP

THOLD

Figure 4. Output Data Setup/Hold Times to ODCK

Silicon Image, Inc.

5

Subject to Change without Notice

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