UT62L64CPC-70 查看數據表（PDF） - Utron Technology Inc
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UT62L64CPC-70 Datasheet PDF : 12 Pages
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UTRON
Rev. 1.4
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
Notes :
1. WE , CE must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a low CE , high CE2, low WE .
3. During a WE controlled write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed on
the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CE low transition and CE2 high transition occurs simultaneously with or after WE low transition, the outputs remain in a high
impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ± 500mV from steady state.
DATA RETENTION CHARACTERISTICS (TA = 0℃ to 70℃/-20℃ to 85℃(E))
PARAMETER
SYMBOL
TEST CONDITION
Vcc for Data Retention
VDR CE ≧VCC-0.2V or CE2 ≤ 0.2V
Data Retention Current
Vcc=2V
-L
IDR
CE ≧VCC-0.2V or CE2 ≤ 0.2V -LL
Chip Disable to Data
Retention Time
tCDR
See Data RetentionWaveforms
(below)
Recovery Time
tR
tRC* = Read Cycle Time
DATA RETENTION WAVEFORM
MIN.
2.0
-
-
0
tRC*
TYP.
-
1
0.5
MAX.
5.5
50
10
UNIT
V
µA
µA
-
-
ns
-
-
ns
Low Vcc Data Retention Waveform (1) ( CE controlled)
VCC
CE
Vcc(min.)
tCDR
VIH
VDR ≧ 2V
CE ≧ VCC-0.2V
Low Vcc Data Retention Waveform (2) (CE2 controlled)
Vcc(min.)
tR
VIH
VCC
CE2
VCC(min.)
tCDR
VIL
VDR ≧ 2V
CE2 ≦ 0.2V
VCC(min.)
tR
VIL
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
7
P80028
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