SPT7722 查看數據表（PDF） - Fairchild Semiconductor
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SPT7722 Datasheet PDF : 12 Pages
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SPT7722
DATA SHEET
Electrical Specifications
(TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle,
ƒIN = 70MHz, dual channel mode; unless otherwise noted)
Parameter
Conditions
Test
Level
Pipeline Delay (Latency)
Single Channel Mode
V
Demuxed Interleaved Mode
V
Demuxed Parallel Mode
Channel B
V
Channel A
V
CLK to DCLKOUT Delay Time
Single Channel Mode (tpd2)
IV
Dual Channel Mode (tpd3)
IV
Output Delay (Clock to DClock)
V
Dynamic Performance
Effective Number of Bits (ENOB)
ƒIN = 70MHz
+25°C
VI
ƒIN = 70MHz
-40°C to +85°C
IV
Signal-to-Noise Ratio (SNR)
ƒIN = 70MHz
+25°C
VI
ƒIN = 70MHz
-40°C to +85°C
IV
Total Harmonic Distortion (THD)
ƒIN = 70MHz
+25°C
VI
ƒIN = 70MHz
-40°C to +85°C
IV
Signal-to-Noise & Distortion (SINAD)
ƒIN = 70MHz
+25°C
VI
ƒIN = 70MHz
-40°C to +85°C
IV
Power Supply Requirements
AVCC Voltage (Analog Supply)
OVDD Voltage (Digital Supply)
AVCC Current
AVCC Current Powerdown
OVDD Current
Single Mode
IV
IV
VI
+25°C
VI
OVDD = 3.0V, 10pF load
V
Parallel Mode
V
Interleave Mode
V
Power Dissipation
VI
Common Mode Reference Output
Voltage
VI
Voltage Tempco
V
Output Impedance
IOUT = ±50 µA
V
Power Supply Rejection Ratio
V
Min.
5.0
5.6
6.4
6.25
44.3
42.6
40.2
39.3
4.75
2.75
2.44
Typ.
2.5
2.5
2.5
3.5
5.18
5.73
18.1
7.0
6.8
46.1
45.4
-47
-45.5
43.7
42.8
5.0
85
4.8
35
55
55
425
2.5
84
1.07
47.5
Max.
Unit
Cycle
Cycle
Cycle
Cycle
5.3
ns
5.9
ns
ps/°C
Bits
Bits
dB
dB
-41.5
dB
-40.3
dB
dB
dB
5.25
V
5.25
V
110
mA
5.5
mA
mA
mA
mA
550
mW
2.56
V
ppm/°C
kΩ
mV/V
NOTE: All electrical characteristics are subject to the following condition:
All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific devices testing actually performed
during production and quality assurance inspection. Any blank section in the data column indicates that the specification is not tested at the
specified condition.
Rev. 1.0.2 December 2002
3
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