SPT7938 查看數據表（PDF） - Cadeka Microcircuits LLC.
零件编号
产品描述 (功能)
比赛名单
SPT7938 Datasheet PDF : 10 Pages
| |||
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
VDD ............................................................................ +6 V
Input Voltages
Analog Input .................................... –0.5 V to VDD +0.5 V
CLK Input ................................................................... VDD
AGND – DGND .................................................. ±100 mV
Temperature
Operating Temperature ............................. –40 to +85 °C
Junction Temperature ......................................... +175 °C
Lead Temperature, (soldering 10 seconds) ........ +300 °C
Storage Temperature ............................... –65 to +150 °C
Output
Digital Outputs ....................................................... 10 mA
Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, VDD=+5.0 V, ƒS=40 MSPS, VIN=0 to 4 V, VRHS=4.0 V, VRLS=0.0 V, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
SPT7938
MIN
TYP
MAX UNITS
Resolution
12
Bits
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
No Missing Codes
V
±3
LSB
V
±1
LSB
VI
Guaranteed
Analog Input
Input Voltage Range
Input Resistance
Input Capacitance
Input Bandwidth
–Full-Scale Error1
+Full-Scale Error1
VIN = 2 VPP
VI
VRLS
V
25
V
5.0
V
250
V
0.035
V
–0.12
VRHS
V
kΩ
pF
MHz
%FS
%FS
Conversion Characteristics
Maximum Conversion Rate
Minimum Conversion Rate
Pipeline Delay (Latency)
Aperture Delay Time
Aperture Jitter Time
Over-Voltage Recovery Time2
VI
40
V
1
IV
V
1.0
V
5.0
MHz
MHz
14
Clock Cycles
ns
ps(p-p)
25 ns
Reference Input
Resistance
Voltage Range
VRHS
VRLS
VRHS – VRLS
VI
420
465
IV
3.0
IV
0.0
V
2.0
4.0
520 Ω
VDD V
2.0 V
5.0 V
Dynamic Performance
Effective Number of Bits
ƒIN=3.58 MHz
TA = +25 °C
I
9.9
10.1
Bits
ƒIN=3.58 MHz
TA = TMIN to TMAX
IV
9.4
10.1
Bits
Signal-to-Noise Ratio
(without Harmonics)
ƒIN=3.58 MHz
TA = +25 °C
I
61.2
62.5
dB
ƒIN=3.58 MHz
TA = TMIN to TMAX
IV
58.0
62.5
dB
1 The full-scale range spans the reference ladder sense pins, VRHS and VRLS. Refer to the Voltage Reference section for discussion.
2 Due to internal architecture, over-voltage recovery time is less than one clock cycle (i.e., 25 ns at ƒCLK = 40 MHz).
SPT7938
2
5/24/00
Share Link: 