MD82C288-10 查看數據表（PDF） - Intel

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MD82C288-10

BUS CONTROLLER FOR M80286 PROCESSORS

Intel 

M82C288

Figures 6 through 10 show the basic command and

control output timing for read and write bus cycles

Halt bus cycles are not shown since they activate no

outputs The basic idle-read-idle and idle-write-idle

bus cycles are shown The signal label CMD repre-

sents the appropriate command output for the bus

cycle For Figures 6 through 10 the CMDLY input is

connected to GND and CENL to VCC The effects of

CENL and CMDLY are described later in the section

on control inputs

Figures 6 7 and 8 show non-MULTIBUS I cycles

MB is cnonected to GND while CEN is connected to

VCC Figure 6 shows a read cycle with no wait states

while Figure 7 shows a write cycle with one wait

state The READY input is shown to illustrate how

wait states are added

Figure 6 Idle-Read-Idle Bus Cycles with MB e 0

271077 – 6

Figure 7 Idle-Write-Idle Bus Cycles with MB e 0

271077 – 7

7

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