MD82C288-10 查看數據表（PDF） - Intel

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MD82C288-10

BUS CONTROLLER FOR M80286 PROCESSORS

Intel 

M82C288

Figure 10 Idle-Write-Idle Bus Cycles with 2 Wait States and with MB e 1

271077 – 10

The MB control input affects the timing of the com-

mand and DEN outputs These outputs are automat-

ically delayed in MULTIBUS I mode to satisfy three

requirements

1) 50 ns minimum setup time for valid address be-

fore any command output becomes active

2) 50 ns minimum setup time for valid write data be-

fore any write command output becomes active

3) 65 ns maximum time from when any read com-

mand becomes inactive until the slave’s read

data drivers read 3-state OFF

Back to back bus cycles with MB e 1 do not change

the timing of any of the command or control outputs

DEN always becomes inactive between bus cycles

with MB e 1

Except for a halt or shutdown bus cycle ALE will be

issued during the second half of TS for any bus cy-

cle ALE becomes inactive at the end of the TS to

allow latching the address to keep it stable during

the entire bus cycle The address outputs may

change during Phase 2 of any TC bus state ALE is

not affected by any control input

Three signal transitions are delayed by MB e 1 as

compared to MB e 0

1) The HIGH to LOW transition of the read com-

mand outputs (IORC MRDC and INTA) are de-

layed one CLK cycle

2) The HIGH to LOW transition of the write com-

mand outputs (IOWC nd MWTC) are delayed two

CLK cycles

3) The LOW to HIGH transition of DEN of write cy-

cles is delayed one CLK cycle

Figure 11 shows how MCE is timed during interrupt

acknlwedged (INTA) bus cycles MCE is one CLK

cycle longer than ALE to hold the cascade address

from a master M8259A valid after the falling edge of

ALE With the exception of the MCE control output

an INTA bus cycle is identical in timing to a read bus

cycle MCE is not affected by any control input

9

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