T80C5112 查看數據表（PDF） - Atmel Corporation

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T80C5112

8-bit Microcontroller with A/D converter

Atmel Corporation 

T80C5112

6.4.2.2. IDLE MODES :

· IDLE modes are achieved by using any instruction that writes into PCON.0 sfr

· IDLE modes A and B depend on previous software sequence, prior to writing into PCON.0 register :

· IDLE MODE A : Xtal_Osc is running (OSCAEN = 1) and selected (CKS = 1)

· IDLE MODE B : RC_Osc is running (OSCBEN = 1) and selected (CKS = 0)

· The unused oscillator Xtal_Osc or RC_Osc can be stopped by software by clearing OSCAEN or OSCBEN

respectively.

· Exit from IDLE mode is acheived by Reset, or by activation of an enabled interrupt.

· In both case, PCON.0 is cleared by hardware.

· Exit from IDLE modes will leave the ocillators control bits OSCAEN, OSCBEN and CKS unchanged.

6.4.2.3. POWER DOWN MODES :

· POWER DOWN modes are achieved by using any instruction that writes into PCON.1 sfr

· Exit from POWER DOWN mode is acheived either by an harware Reset, by an external interruption.

· By RST signal : The CPU will restart in the mode defined by RST_OSC.

· By INT0 or INT1 interruptions, if enabled. The ocillators control bits OSCAEN, OSCBEN and CKS will

not be changed, so the selected oscillator before entering into Power-down will be activated.

RCLF

PD IDLE CKS OSCBEN OSCAEN

_OFF

Selected Mode

Comment

0

0

1

X

1

X

NORMAL MODE A

OSCA: XTAL clock

X

X

1

X

0

1

INVALID

no active clock

0

0

1

0

0

0

RESCUE MODE

OSCC: Low speed RC clock active

0

0

0

1

X

X

NORMAL MODE B,

OSCB: high speed RC clock

X

X

0

0

X

1

INVALID

0

0

0

0

0

0

RESCUE MODE

OSCC: Low speed RC clock active

0

1

1

X

1

X

IDLE MODE A

The CPU is off, OSCA supplies the

peripherics

0

1

0

1

X

X

IDLE MODE B

The CPU is off, OSCB supplies the

peripherics

1

X

X

X

1

0

POWER DOWN MODE The CPU and peripherics are off, but

with WD

OSCC is still running for WD

The CPU is off, OSCA and OSCB are

1

X

X

X

X

1

TOTAL POWER DOWN stopped

OSCC is stopped

6.4.2.4. Prescaler Divider :

· An hardware RESET selects the prescaler divider :

· CKRL = FFh: internal clock = OscOut / 2 (Standard C51 feature)

· X2 = 0,

· SEL_OSC signal selects Xtal_Osc or RC_Osc, depending on the value of the RST_OSC configuration bit.

· After Reset, any value between FFh down to 00h can be written by software into CKRL sfr in order to divide

frequency of the selected oscillator:

· CKRL = 00h : minimum frequency = OscOut / 512

· CKRL = FFh : maximum frequency = OscOut / 2

10

Rev. B - November 10, 2000

Preliminary

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