MP8799AE 查看數據表（PDF） - Exar Corporation

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MP8799AE

Very Low Power, 1 MSPS, 10-Bit Analog-to-Digital Converter with 8-Channel Mux

Exar Corporation 

MP8799

tR

tF

tS

tB

CLOCK

SAMPLE

N–1

AUTO SAMPLE

BALANCE

N

VIH

VIL

AUTO

SAMPLE

BALANCE

N+1

when φS disconnects the latches from the comparators. This de-

lay is called aperture delay (tAP).

The coarse comparators make the first pass conversion and

selects a ladder range for the fine comparators. The fine compa-

rators are connected to the selected range during the next φB

phase.

ANALOG

TS

INPUT

DATA

VOH

VOL

N-1

tDL

tHLD

Figure 1. MP8799 Timing Diagram

φS

VIN

VTAP

Ref

Ladder

φB

φS

VIN

VTAP

φB

φS

Latch

COARSE COMPARATOR

φS

φB

Latch

THEORY OF OPERATION

Analog-to-Digital Conversion

The MP8799 converts analog voltages into 1024 digital

Selected

φB

Range

FINE COMPARATOR

Figure 2. MP8799 Comparators

codes by encoding the outputs of 15 coarse and 67 fine compa-

rators. Digital logic is used to generate the overflow bit. The con- AIN Sampling, Ladder Sampling, and Conversion Timing

version is synchronous with the clock and it is accomplished in 2

clock periods.

The reference resistance ladder is a series of 1025 resistors.

The first and the last resistor of the ladder are half the value of

the others so that the following relations apply:

RREF = 1024 ∗ R VREF = VREF(+) – VREF(–) = 1024 ∗ LSB

The clock signal generates the two internal phases, φB (CLK

high) and φS (CLK low = sample) (See Figure 2.). The rising

edge of the CLK input marks the end of the sampling phase (φS).

Internal delay of the clock circuitry will delay the actual instant

Figure 3. shows this relationship as a timing chart. AIN sam-

pling, ladder sampling and output data relationships are shown

for the general case where the levels which drive the ladder

need to change for each sampled AIN time point. The ladder is

referenced for both last AIN sample and next AIN sample at the

same time. If the ladder’s levels change by more than 1 LSB,

one of the samples must be discarded. Also note that the clock

low period for the discarded AIN can be reduced to the minimum

tS time of 150 ns.

Short Cycle Sample will be discarded

Hold Reference Value Past

Clock Change for tAP Time

tS

External

Update

References

Settle by Clock Update Time

Reference Stable Time – For Sample AIN1

Reference Stable Time – For Sample AIN2

Clock

Internal

AIN Sample

Window

Ladder Sample

Window (MSB Bank)

AINX0

Sample AIN1

FB

FS

Sample AIN1

Sample Ladder

for AIN1

AINX1

Not

FB

Used

FS

AINX1

Sample AIN2

FB

FS

Sample AIN2

Sample Ladder

for AINX1

Sample Ladder

for AIN2

Sample Ladder

for AINX2

Ladder Compare

(LSB Bank)

External

DATA

Rev. 3.00

Compare Ladder

V/S AINX0

Compare Ladder

V/S AIN1

Compare Ladder

V/S AINX1

DATA AIN0

DATA AINX0

DATA AIN1

Not Used

Figure 3. AIN Sampling, Ladder Sampling & Conversion Timing

Compare Ladder

V/S AIN2

DATA AINX1

Not Used

6

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