LC11014-241 查看數據表（PDF） - SANYO -> Panasonic
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LC11014-241 Datasheet PDF : 13 Pages
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LC11014-241
Symbol
SRD0 [7:0]
SRD1 [7:0]
SGD0 [7:0]
SGD1 [7:0]
SBD0 [7:0]
SBD1 [7:0]
SHSYNC
SVSYNC
SHDEN
SCTL
CLKSEL
CLK
CLKB
RD0 [0:5]
RD1 [0:5]
GD0 [0:5]
GD1 [0:5]
BD0 [0:5]
BD1 [0:5]
HSYNC
VSYNC
HDEN
CTL
PWRSV
BYPASS
TEST [0:3]
NC
Pin No.
I/O
Function
86 to 89, 92 to 95
I
96 to 99, 101 to 104
I
105 to 107,
110 to 114
Input pins for red, green and blue gray-scale data. SRD07, SRD17, SGD07, SGD17, SBD07, SBD17 are
I
the MSBs. SRD00, SRD10, SGD00, SGD10, SBD00, SBD10 are the LSBs. Input data 00H corresponds
to minimum brightness, and FFH to maximum brightness. Note that correct gray-scale display does not
115 to 117,
119 to 123
occur when an input is set to either the minimum or maximum. If 2-pixel data is set on both S×D0 and
I
S×D1, the display data on S×D0 is displayed first. In input/output modes 1 and 2, inputs SRD1[0:7],
SGD1[0:7] and SBD1[0:7] should be tied high or low.
124, 125, 128 to 133
I
134, 136 to 142
I
79
I
Horizontal and vertical synchronization signal inputs. These are the sources for the HSYNC and VSYNC
80
I
signals. They are also used to control data processing. Active-low signals.
78
I
Horizontal data valid-period signal input. Set this pin high during periods when the horizontal data is
valid. If this signal is not used, tie it high and set the input data to 0 during the horizontal blanking period.
LCD control signal input. Input control signal that must be matched to the data signal timing. This is the
83
I source for the CTL signal. If the CTL signal is not used, there is no internal signal processing of this input
and hence there is no need to input the SCTL signal.
8
I
CLKSEL is the dot clock output select pin. It is used to select the output mode of the dot clock signal
output pin.
66
O
In input/output modes 0 and 2: When CLKSEL is low, a signal with the opposite phase from SCLK is
output from CLK. When CLKSEL is high, a signal with the same phase as SCLK is output from CLKB.
In input/output mode 1: When CLKSEL is low, a signal with half the frequency of SCLK is output from
69
O CLK. When CLKSEL is high, a signal with the opposite phase from CLK is output from CLKB.
52 to 53, 56 to 59
44 to 47, 50, 51
34, 35, 38 to 41
26 to 28, 31 to 33
17, 20 to 23, 25
10, 11, 13 to 16
O Red, green and blue gray-scale data output pins. RD05, RD15, GD05, GD15, BD05, BD15 are the
MSBs. RD00, RD10, GD00, GD10, BD00, BD10 are the LSBs. If a 2-pixel data set is on ×D0 and ×D1,
O the data on ×D0 is displayed first. In input/output modes 1 and 2, outputs RD1[0:5], GD1[0:5] and
BD1[0:5] are low.
O In 3-bit data output mode: RD03, RD13, GD03, GD13, BD03, BD13 are the LSBs. RD0[2:0], RD1[2:0],
O GD0[2:0], GD1[2:0], BD0[2:0], BD1[2:0] are low.
In 4-bit data output mode: RD02, RD12, GD02, GD12, BD02, BD12 are the LSBs. RD0[1:0], RD1[1:0],
O GD0[1:0], GD1[1:0], BD0[1:0], BD1[1:0] are low.
In 3-bit data output mode: RD01, RD11, GD01, GD11, BD01, BD11 are the LSBs. RD0[0], RD1[0],
O GD0[0], GD1[0], BD0[0], BD1[0] are low.
62
O Vertical and horizontal synchronization signal outputs. To match the data signal timing, these outputs are
delayed with respect to their input signals. In input/output mode 0, they are delayed by 8 SCLK cycles,
and in input/output modes 1 and 2, they are delayed by 16 SCLK cycles. When PWRSV is high, these
63
O signals are output without being latched internally.
Horizontal data valid-period signal output.To match the data signal timing, this output is delayed with
64
O
respect to the input signal. In input/output mode 0, they are delayed by 8 SCLK cycles, and in
input/output modes 1 and 2, they are delayed by 16 SCLK cycles. When PWRSV is high, this signal is
output without being latched internally.
LCD control signal output. To match the data signal timing, this output is delayed with respect to the
70
O
SCTL input signal. In input/output mode 0, they are delayed by 8 SCLK cycles, and in input/output modes
1 and 2, they are delayed by 16 SCLK cycles. When PWRSV is high, this signal is output without being
latched internally.
Power-save control input. When this input goes high, the internal clock stops and the LSI enters power-
84
I save mode. Output data are held high. VSYNC, HSYNC, HDEN and CTL control signals, and either CLK
or CLKB are output without being latched internally. Tie low or leave open for normal operation.
Gray-scale processing bypass pin. When high, the input signals are latched and output without change.
85
I When a high-level input on this pin is sampled on the falling edge of SCLK: in input/output mode 0, output
is delayed by 8 SCLK cycles, and in input/output modes 1 and 2, output is delayed by 16 SCLK cycles.
4 to 7
I Test pins [0:3]; left open for normal operation
71
– Must be left open.
No. 5578—5/13
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