UM61512A 查看數據表（PDF） - UMC Corporation
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UM61512A Datasheet PDF : 16 Pages
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UM61512A Series
64K X 8 BIT HIGH SPEED CMOS SRAM
Features
Single +5V power supply
Access times: 15/20/25ns (max.)
Current: Operating: 160mA (max.)
Standby: 10mA (max.)
Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL compatible
Common I/O using three-state output
Output enable and two chip enable inputs for easy
application
Data retention voltage: 3V (min.)
Available in 32-pin SKINNY DIP, TSOP, SOP, SOJ
and both 300/400 mil packages
General Description
The UM61512A is a low operating current 524,288-bit
static random access memory organized as 65,536
words by 8 bits and operates on a single 5V power
supply. It is built using UMC's high performance CMOS
process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Pin Configurations
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 3V.
SKINNY/SOJ/SOP
NC
1
NC
2
A14
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
I/O1
13
I/O2
14
I/O3
15
GND
16
32 VCC
31
A15
30
CE2
29
WE
28
A13
27
A8
26 A9
25
A11
24
OE
23
A10
22 CE1
21
I/O8
20
I/O7
19
I/O6
18
I/O5
17
I/O4
TSOP (forward type)
16
1
17
32
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
NC
A14
A12
A7
A6
A5
A4
Pin No.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin
Name
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
I/O4
I/O5
I/O6
I/O7
I/O8
CE1
A10
OE
1
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