UM61512A 查看數據表（PDF） - UMC Corporation

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UM61512A

64K X 8 BIT HIGH SPEED CMOS SRAM

UMC Corporation 

UM61512A

Timing Waveforms (continued)

Read Cycle 4(1)

Address

OE

CE1

CE2

DOUT

tRC

tAA

tOE

tOLZ5

tACE1

tCLZ25

tACE2

tCLZ25

tOH

tCHZ15

tOHZ5

tCHZ25

Notes: 1. WE is high for Read Cycle.

2. Device is continuously enabled CE1 = VIL and CE2 = VIH.

3. Address valid prior to or coincident with CE1 transition low.

4. OE = VIL.

5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

6. CE2 is high.

7. CE1 is low.

8. Address valid prior to or coincident with CE2 transition high.

7

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