UPD16835 查看數據表（PDF） - NEC => Renesas Technology

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UPD16835

MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT

NEC => Renesas Technology 

µPD16835

<2nd byte>

The 2nd byte specifies the delay between data being read and data being output. This delay is called the start up

wait time, and the motor can be driven from that point at which the start up wait time is “0”. This time is counted at the

rising edge of VD. The start up wait time can be set to 65.28 ms (when a 4-MHz clock is input), and can be fine-tuned

by means of 8-bit division (256-µs step: with 4-MHz clock). The start up wait time is set to 65.28 ms when all the bits

of the 2nd byte are set to “1”.

Caution Always input data other than “0” to this byte because the start up wait time is necessary for latching

data. If “0” is input to this byte, data cannot be updated. Transfer standard data during the start up

wait time.

<3rd byte>

The 3rd byte specifies the delay between the start point wait time being cleared and the output pulse being

generated. This time is called the start up drive wait time, and the output pulse is generated from the point at which

the start up drive wait time reaches “0”. The start up drive wait time is counted at the falling edge of the start up wait

time. The start up drive wait time can be set to 65.28 ms (with 4-MHz clock) and can be fine-tuned by means of 8-bit

division (256-µs step: with 4-MHz clock). The start up drive wait time is set to 65.28 ms when all the bits of the 3rd

byte are “1”.

Caution Always input data other than “0” to this byte because the start up drive wait time is necessary for

latching data. If “0” is input to this byte, data cannot be updated.

<4th byte>

The 4th byte selects a chopping frequency by using 5-bit data. It also selects whether the chopping frequency is

created by dividing the original oscillation (external clock) or whether the internal oscillator is used. The chopping

frequency is selected by bits D0 to D4. Bit D7 specifies the method used to create the chopping frequency. When this

bit is “0”, the original oscillation (external clock input to OSCIN) is used; when it is “1”, the internal oscillator is used.

Bits D5 and D6 are fixed to “0”.

The chopping signal is output after the initial data has been input and the first standard data has been latched (see

Timing Chart).

Table 5-3. 4th Byte Data Configuration (Initial data)

Bit

D7

D6

Data

0 or 1

0

D5

D4

D3

D2

D1

D0

0

0 or 1 0 or 1 0 or 1 0 or 1 0 or 1

The chopping frequency is set to 0 kHz and to a value in the range of 32 to 124 kHz (in 4-kHz steps), as follows.

Although the chopping frequency is set by 5 bits of data, it is internally configured using 7-bit data (with the low-

order 2 bits fixed to 0).

Data Sheet G11594EJ2V0DS00

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