UPD16835 查看數據表（PDF） - NEC => Renesas Technology

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UPD16835

MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT

NEC => Renesas Technology 

µPD16835

(Data Update Timing)

The standard data (pulse width, number of pulses, rotation direction, current setting, and ENABLE) of this product

are set and updated at the following latch timing.

Table 5-14. Data Update Timing

ENABLE change

Pulse width

Number of pulses

Rotation direction

Current setting

ENABLE

1→1

FF2↓

FF2↓

FF2↓

FF2↓

FF2↓

0→1

FF2↓

FF2↓

FF2↓

FF1↓

FF1↓

1→0

FF2↓

FF2↓

FF2↓

FF2↓

FF2↓

0→0

-

-

-

-

-

The timing at which data is to be updated differs, as shown in Table 5-14, depending on the enabled status.

For example, suppose the enable signal is currently “0” (output high impedance) and “1” (output conduction) is input

by the next data. In this case, the pulse width, number of pulses, and rotation direction signals are updated at

FF2(upon the completion of start up wait), and the current setting and ENABLE signals are updated at FF1 (upon

completion of start up drive wait).

VD

FF1

Start up wait

FF2

Start up wait +

start up drive wait

Pulse output

Pulse width, number of pulses, and rotation direction

are updated.

Current setting and ENABLE are updated

(ENABLE change: 0 to 1).

VD

LATCH

(1)

I1

(2)

S1

(3)

S2

S3

Initial data

identification

Standard data

identification

I1 data is output.

FF1, FF2 output

Data Sheet G11594EJ2V0DS00

19

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