HSP50016-EV 查看數據表（PDF） - Intersil

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HSP50016-EV

DDC Evaluation Platform

Intersil 

HSP50016-EV

HSP50016-EV Control Panel Software

The HSP50016-EV Control Panel is a graphical user

interface for controlling the operation of the HSP50016-EV

Board via an IBM PC or compatible. The control panel,

shown in Figure 3, supports loading the HSP50016's control

words; setting the state of control inputs; and specifying files

which serve as the sources and destinations for the

HSP50016's data and TAP inputs and outputs. Operation of

the control panel software is dependent on the clock source

provided to the HSP50016-EV as specified in the clock

select portion of the control panel. The HSP50016-EV

Control Panel is invoked by typing:

DDCCTRL <Enter>

Port Configuration

Communication between the Control Panel software and the

evaluation board requires that the software knows which one

of the PC's parallel ports is being used for communication

with the HSP50016-EV and which board address the

HSP50016-EV has been configured for. The default

configuration assumes that LPT1 is being used and that the

HSP50016-EV has been configured for a board address of

0. The Port Configuration can be inspected by opening up

the port configuration window using the F9 function key. As

shown in Figure 4, the window displays the available parallel

ports and their addresses. Also displayed are the current

port and HSP50016-EV board address being used by the

Control Panel software.

The current port and HSP50016-EV address are changed by

opening up the Port Configuration Window, using the

up/down arrow keys to select the desired parameter, and

toggling the space bar to change the selection. Proper

operation of the control panel software requires that the

HSP50016-EV board address specified in the port

configuration window matches the address jumpered in the

Address Selection Section of the HSP50016-EV’s headers

JP6-13.

Clock Select

The Clock Select portion of the control panel is used to tell

the Control Panel software which of four different clock

sources is being supplied to the HSP50016-EV. The choices

include one of two different software generated clocks

(Manual CLK or Port CLK), an oscillator clock provided by

the HSP50016-EV (Oscillator CLK), or an externally

supplied clock (External CLK). The clock mode selected

must be consistent with the Clock Select jumper position in

the HSP50016-EV’s headers JP1-3. If either Manual CLK or

Port CLK are specified in the Control Panel, the clock select

jumper must be inserted in JP3. If either Oscillator CLK or

External CLK is specified, the jumper must be inserted in

JP2 or JP1 respectively.

In Manual CLK mode, single clock pulses are sent to the

HSP50016 by depressing the F2 function key. The clock pulse

is software generated by setting and clearing the PCCLK bit of

the Control Register U16 on the HSP50016-EV. After each

clock the HSP50016-EV's data outputs are inspected to see if

they are ready to be read. If so, the data is read into the PC for

display in the Control Panel. In this mode, file input and output

are supported (See File I/O Select Section).

In Port CLK mode, a free running clock is sent to the

HSP50016. The clock is started and stopped by depressing

the F2 function key. The clock pulses are software generated

by continually setting and clearing the PCCLK bit of Control

Register U16. After each clock the HSP50016-EV's data

outputs are inspected to see if they are ready to be read. If

so, the data is read into the PC for display in the Control

Panel. In this mode, file input and output are supported (see

File I/O Select Section).

In Oscillator CLK mode, the HSP50016 is supplied with a

clock by the oscillator on board the HSP50016-EV. In this

mode, the Control Panel can be used for modifying RESET

and IQSTRT, the control words, and the data and TAP inputs

to the DDC. However, the software is unable to provide file

based I/O to the evaluation board since the data rate

provided by the oscillator is much greater than that possible

through the parallel port of the PC. As a result, the Control

Panel disables file based I/O and the display of DDC output

in this mode.

Operation in External CLK mode is identical to that in

Oscillator CLK mode, except that the HSP50016 is supplied

with a clock through the 96 Pin DIN connector P1 on the

HSP50016-EV. Because this clock is asynchronous to the

PC, file based I/O and the DDC output displays are disabled.

The clocking mode used by the control panel is indicated by

the position of the “check mark” symbol within the Clock

Select portion of the Control Panel. A different clocking

mode may be selected by positioning the “check mark”

symbol in front of the desired clocking mode. The position of

the “check mark” is changed by using the cursor keys to

move the active window to the desired position and then

toggling the space bar to move the “check mark”.

File I/O Select

The File I/O Select portion of the Control Panel allows the

user to specify files which can be used as an input data

source or an output data destination for the HSP50016-EV.

The input data is loaded on to the input bus prior to the

software generated clock and the output data is read from

the output bus following the software generated clock.

If file based input is selected, the Control Panel software

down loads data from the specified file to registers on the

HSP50016-EV and clocks the data into the DATA0-15 inputs

of the DDC. The Loop Count allows the user to simulate long

data streams by repeatedly sending the same input file.

If file based output is specified, the software reads the data

on the I and Q outputs of the HSP50016 and stores the data

in the specified file. The software automatically reads the

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