HSP43220(2004) 查看數據表（PDF） - Intersil
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产品描述 (功能)
比赛名单
HSP43220 Datasheet PDF : 18 Pages
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Pinout
HSP43220
84 PLASTIC LEADED CHIP CARRIER (PLCC)
STARTOUT
VCC
STARTIN
ASTARTIN
RESET
A1
A0
WR
CS
C_BUS 15
C_BUS 14
C_BUS 13
C_BUS 12
C_BUS 11
C_BUS 10
C_BUS 9
VCC
GND
C_BUS 8
C_BUS 7
C_BUS 6
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
12
74
13
73
14
72
15
71
16
70
17
69
18
68
19
67
20
66
21
65
22
64
23
63
24
62
25
61
26
60
27
59
28
58
29
57
30
56
31
55
32
54
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
GND
DATA_OUT 0
DATA_OUT 1
DATA_OUT 2
DATA_OUT 3
DATA_OUT 4
DATA_OUT 5
DATA_OUT 6
DATA_OUT 7
DATA_OUT 8
DATA_OUT 9
DATA_OUT 10
DATA_OUT 11
GND
VCC
DATA_OUT 12
DATA_OUT 13
DATA_OUT 14
DATA_OUT 15
DATA_OUT 16
DATA_OUT 17
Pin Description
NAME TYPE
DESCRIPTION
VCC
GND
CK_IN
FIR_CK
DATA_IN0-
15
C_BUS0-15
DATA_OUT
0-23
DATA_RDY
The +5V power supply pins.
The device ground.
I Input Sample Clock. Operations in the HDF are synchronous with the rising edge of this clock signal. The maximum clock
frequency is 33MHz. CK_IN is synchronous with FIR_CK and thus the two clocks may be tied together if required, or CK_IN
can be divided down from FIR_CK. CK_IN is a CMOS level signal.
I Input Clock for the FIR Filter. This clock must be synchronous with CK_IN. Operations in the FIR are synchronous with the
rising edge of this clock signal. The maximum clock frequency is 33MHz. FIR_CK is a CMOS level signal.
I Input Data Bus. This bus is used to provide the 16-bit input data to the HSP43220. The data must be provided in a synchro-
nous fashion, and is latched on the rising edge of the CK_IN signal. The data bus is in 2's complement fractional format. Bit
15 is the MSB.
I Control Input Bus. This input bus is used to load all the filter parameters. The pins WR, CS and A0, A1 are used to select
the destination of the data on the Control bus and write the Control bus data into the appropriate register as selected by A0
and A1
O Output Data Bus. This 24-Bit output port is used to provide the filtered result in 2's complement format. The upper 8 bits of
the output, DATA_OUT16-23 will provide extension or growth bits depending on the state of OUT_SELH and whether the
FIR has been put in bypass mode. Output bits DATA_OUT0-15 will provide bits 20 through 2-15 when the FIR is not by-
passed and will provide the bits 2-16 through 2-31 when the FIR is in bypass mode.
O An active high output strobe that is synchronous with FIR_CK that indicates that the result of the just completed FIR cycle
is available on the data bus.
2
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