HSP43220(2004) 查看數據表（PDF） - Intersil

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HSP43220
(Rev.:2004)

Decimating Digital Filter

Intersil 

HSP43220

A0-1

WR CS C_BUS

CK_IN RESET

RESET CK_IN ASTARTIN

CONTROL

REGISTER LOGIC

H_DRATE

H_BYP

CLOCK

DIVIDER

ISTART

START

LOGIC

STARTIN

STARTOUT

6

5

5

H_GROWTH INT_EN1-5 COMB_EN1-5

CK DEC

ISTART

H_GROWTH

6

HDF FILTER SECTION

INT_EN1-5

RESET

COMB_EN1-5

5

5

DATA

IN 16

INPUT

REG 16

DATA

SHIFTER 66

INTEGRATOR

26

DEC

REG 26

COMB FILTER

19

RESET

ROUND

16

TO FIR

REG

16

CK_IN

CK_DEC

FIGURE 1. HIGH ORDER DECIMATION FILTER FIGURE

TO FIR

FROM

SHIFTER

66

CK IN

0

MUX

INT_EN5

∑

REG

63

0

MUX

INT_EN4

∑

REG

53

0

MUX

INT_EN3

∑

REG

43

0

MUX

INT_EN2

∑

REG

35

0

MUX

INT_EN1

∑

REG

TO

DECIMATION

REGISTER

26

FIGURE 2. INTEGRATOR

There are three signals that control the integrator section;

they are H_STAGES, H_BYP and RESET. In Figure 2 these

control signals have been decoded and are labelled

INT_EN1 - INT_EN5. The order of the filter is loaded via the

control bus and is called H_STAGES. H_STAGES is

decoded to provide the enables for each integrator stage.

When a given integrator stage is selected, the feedback path

is enabled and the integrator accumulates the current data

sample with the previous sum. The integrator section can be

put in bypass mode by the H_BYP bit. When H_BYP or

RESET is asserted, the feedback paths in all integrator

stages are cleared.

Decimation Register

The output of the Integrator section is latched into the

Decimation Register by CK_DEC. The output of the

Decimation register is cleared when RESET is asserted. The

HDF decimation rate = H_DRATE +1, which is defined as

HDEC for convenience.

Comb Filter Section

The output of the Decimation Register is passed to the

Comb Filter Section. The Comb section consists of 5

cascaded Comb filters or differentiators. Each Comb filter

section calculates the difference between the current and

previous integrator output. Each Comb filter consists of a

register which is clocked by CK_DEC, followed by an

subtractor, where the subtractor calculates the difference

between the input and output of the register. Bit truncations

are done at each stage as shown in Figure 3. The first

stage bit width is 26 bits and the output of the fifth stage is

19 bits.

There are three signals that control the Comb Filter; H_

STAGES, H_BYP and RESET. In Figure 3 these control

signals are decoded as COMB_EN1 - COMB_EN5. The

order of the Comb filter is controlled by H_STAGES, which is

programmed over the control bus. H_BYP is used to put the

comb section in bypass mode. RESET causes the register

output in each Comb stage to be cleared. The H_ BYP and

RESET control pins, when asserted force the output of all

registers to zero so data is passed through the subtractor

unaltered. When the H_STAGES control bits enable a given

stage the output of the register is subtracted from the input.

4

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