W149(2000) 查看數據表（PDF） - Cypress Semiconductor

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W149
(Rev.:2000)

440BX AGPset Spread Spectrum Frequency Synthesizer

Cypress Semiconductor 

W149

DC Electrical Characteristics: (continued) TA = 0°C to +70°C; VDDQ3 = 3.3V±5%; VDDQ2 = 2.5V±5%

Parameter

Description

Test Condition

Min.

Typ.

Max. Unit

Crystal Oscillator

VTH

X1 Input threshold Voltage[6]

CLOAD

Load Capacitance, Imposed on

External Crystal[7]

CIN,X1

X1 Input Capacitance[8]

Pin Capacitance/Inductance

VDDQ3 = 3.3V

Pin X2 unconnected

1.65

V

14

pF

28

pF

CIN

Input Pin Capacitance

Except X1 and X2

5

pF

COUT

Output Pin Capacitance

6

pF

LIN

Input Pin Inductance

7

nH

Notes:

6. X1 input threshold voltage (typical) is VDDQ3/2.

7. The W149 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is

14 pF; this includes typical stray capacitance of short PCB traces to crystal.

8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).

AC Electrical Characteristics

TA = 0°C to +70°C; VDDQ3 = 3.3V±5%; VDDQ2 = 2.5V±5%; fXTL = 14.31818 MHz

AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the

clock output; Spread Spectrum clocking is disabled.

CPU Clock Outputs, CPU_F, CPU1 (Lump Capacitance Test Load = 20 pF)

CPU = 66.6 MHz CPU = 100 MHz

Parameter

Description

Test Condition/Comments

Min. Typ. Max. Min. Typ. Max. Unit

tP

Period

tH

High Time

Measured on rising edge at 1.25V

15

Duration of clock cycle above 2.4V, at 5.6

min. edge rate (1.5 V/ns)

15.5 10

3.3

10.5 ns

ns

tL

Low Time

Duration of clock cycle below 0.4V, at 5.3

3.1

ns

min. edge rate (1.5 V/ns)

tR

Output Rise Edge Rate Measured from 0.4V to 2.4V

1.5

4 1.5

4 V/ns

tF

Output Fall Edge Rate Measured from 2.4V to 0.4V

1.5

4 1.5

4 V/ns

tD

Duty Cycle

Measured on rising and falling edge at 45

1.5V, at min. edge rate (1.5 V/ns)

55 45

55 %

tJC

Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Max-

200

imum difference of cycle time between

two adjacent cycles.

200 ps

tSK

Output Skew

Measured on rising edge at 1.5V

250

fST

Frequency Stabiliza- Assumes full supply voltage reached

3

tion from Power-up

within 1 ms from power-up. Short cycles

(cold start)

exist prior to frequency stabilization.

250 ps

3 ms

Zo

AC Output Impedance Average value during switching transi-

20

tion. Used for determining series termi-

nation value.

20

Ω

10

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