W83195BR-101 查看數據表（PDF） - Winbond

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W83195BR-101

Winbond Clock Generator For Intel 915/925 Chipsets

Winbond 

W83195BR/G-101

STEPLESS FOR INTEL 915/925 CHIPSETS

Table-2 CPU, SRC, PCI divider ratio selection Table

LSB

MSB

Bit2/

0

Bit4/

Bit6

1

00

Div2

Div0

01

Div3

Div0

CPU

Bit1, 0

10

Div4

Div0

11

Div6

Div0

7.14 Register 13: Step-less Enable Control (Default: 0Fh)

BIT

NAME

PWD

DESCRIPTION

7 EN_MN_PROG

6 N<10>

5 Reserved

4 Reserved

3 IVAL<3>

0: Output frequency depend on frequency table

1: Program all clock frequency by changing M/N value

The equation is

0 VCO =14.318MHz*(N+4)/ M.

Once the watchdog timer timeout, the bit will be clear.

Then the frequency will be decided by hardware default

FS<2:0> or desired frequency select SAF_FREQ [4:0]

depend on EN_SAFE_FREQ (Reg0 - bit 0).

0 Programmable N divisor bit 10.

0 Reserved

0 Reserved

1

2 IVAL<2>

1 IVAL<1>

1

Charge pump current selection

1

0 IVAL<0>

1

TYPE

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

- 13 -

Publication Release Date: March 2006

Revision 0.7

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