W83195BG-101 查看數據表（PDF） - Winbond

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W83195BG-101

Winbond Clock Generator For Intel 915/925 Chipsets

Winbond 

W83195BR/G-101

STEPLESS FOR INTEL 915/925 CHIPSETS

Tables of Content-

1. GENERAL DESCRIPTION ......................................................................................................... 1

2. PRODUCT FEATURES .............................................................................................................. 1

3. PIN CONFIGURATION ............................................................................................................... 2

4. BLOCK DIAGRAM ...................................................................................................................... 3

5. PIN DESCRIPTION..................................................................................................................... 4

5.1 Crystal I/O...................................................................................................................................4

5.2 CPU, SRC, PCIF, and PCI Clock Outputs................................................................................4

5.3 Frequency select, and Fixed Frequency Outputs.....................................................................5

5.4 I2C Control Interface..................................................................................................................5

5.5 Power Management Pins ..........................................................................................................6

5.6 Power Pins .................................................................................................................................6

6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 7

7.

I2C CONTROL AND STATUS REGISTERS............................................................................... 8

7.1 Register 0: Frequency Select Register (Default = 10h)............................................................8

7.2 Register 1: CPU Clock Control (1 = Enable, 0 = Stopped) (Default: E7h)...............................8

7.3 Register 2: PCI Clock Control (1 = Enable, 0 = Stopped) (Default: FFh) ................................9

7.4 Register 3: PCI Clock Control (1 = Enable, 0 = Stopped) (Default: FFh) ................................9

7.5 Register 4: 48MHz, DOT, REF Control (1 = Enable, 0 = Stopped) (Default: FFh)..................9

7.6 Register 5: Watchdog Control (Default: 02h) ..........................................................................10

7.7 Register 6: SRC Control (1 = Enable, 0 = Stopped) (Default: FEh).......................................10

7.8 Register 7: Winbond Chip ID (Default: 22h) (Read Only).......................................................10

7.9 Register 8: M/N Program (Default: D0h).................................................................................11

7.10 Register 9: M/N Program Register (Default: 7Ah) ..................................................................11

7.11 Register 10: Reserved (Default: 3Bh) .....................................................................................12

7.12 Register 11: Spread Spectrum Programming (Default: 0Bh).................................................12

7.13 Register 12: Divisor Control (Default: 72h) .............................................................................12

7.14 Register 13: Step-less Enable Control (Default: 0Fh) ............................................................13

7.15 Register 14: Control (Default: 10h)..........................................................................................14

7.16 Register 15: Reserved (Default: ECh).....................................................................................14

7.17 Register 16: Skew Control (Default: E4h) ...............................................................................14

7.18 Register 17: Reserved (Default: 00h)......................................................................................14

7.19 Register 18: Reserved (Default: 00h)......................................................................................14

7.20 Register 19: Reserved (Default: DAh).....................................................................................15

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