WM8591 查看數據表（PDF） - Wolfson Microelectronics plc

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WM8591

24-bit, 192kHz Stereo CODEC

Wolfson Microelectronics plc 

WM8591

TABLE OF CONTENTS

Production Data

DESCRIPTION .......................................................................................................1

FEATURES.............................................................................................................1

APPLICATIONS .....................................................................................................1

BLOCK DIAGRAM .................................................................................................1

TABLE OF CONTENTS .........................................................................................2

PIN CONFIGURATION...........................................................................................3

ORDERING INFORMATION ..................................................................................3

ABSOLUTE MAXIMUM RATINGS.........................................................................5

ELECTRICAL CHARACTERISTICS ......................................................................6

TERMINOLOGY ............................................................................................................ 8

MASTER CLOCK TIMING......................................................................................9

DIGITAL AUDIO INTERFACE – MASTER MODE ......................................................... 9

DIGITAL AUDIO INTERFACE – SLAVE MODE .......................................................... 10

CONTROL INTERFACE TIMING – 2-WIRE SERIALCONTROL ................................. 12

DEVICE DESCRIPTION.......................................................................................13

INTRODUCTION ......................................................................................................... 13

AUDIO DATA SAMPLING RATES............................................................................... 13

ZERO DETECT ........................................................................................................... 15

POWERDOWN MODES ............................................................................................. 15

INTERNAL POWER ON RESET CIRCUIT.................................................................. 16

DIGITAL AUDIO INTERFACE ..................................................................................... 18

CONTROL INTERFACE OPERATION ........................................................................ 22

CONTROL INTERFACE REGISTERS ........................................................................ 23

ADC/DAC SYNCHRONIZATION ................................................................................. 32

LIMITER / AUTOMATIC LEVEL CONTROL (ALC) ...................................................... 33

REGISTER MAP ......................................................................................................... 37

DIGITAL FILTER CHARACTERISTICS ...............................................................44

DAC FILTER RESPONSES......................................................................................... 45

ADC FILTER RESPONSES......................................................................................... 46

ADC HIGH PASS FILTER ........................................................................................... 46

DIGITAL DE-EMPHASIS CHARACTERISTICS........................................................... 47

APPLICATIONS INFORMATION .........................................................................48

RECOMMENDED EXTERNAL COMPONENTS .......................................................... 48

USE OF ADC/DAC SYNCHRONIZER ......................................................................... 49

PACKAGE DIMENSIONS ....................................................................................50

IMPORTANT NOTICE ..........................................................................................51

ADDRESS: .................................................................................................................. 51

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PD Rev 4.0 December 2005

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