W48S87-72X 查看數據表（PDF） - Cypress Semiconductor
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W48S87-72X Datasheet PDF : 19 Pages
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W48S87-72
Serial Input Port
Parameter
Description
fSCLOCK
tSTHD
tLOW
tHIGH
tDSU
tDHD
SCLOCK Frequency
Start Hold Time
SCLOCK Low Time
SCLOCK High Time
Data Set-up Time
Data Hold Time
tR
tF
tSTSU
tSPF
tSP
Rise Time, SDATA and
SCLOCK
Fall Time, SDATA and
SCLOCK
Stop Set-up Time
Bus Free Time between
Stop and Start Condition
Allowable Noise Spike
Pulse Width
Test Condition
Normal Mode
(Transmitter should provide a 300-ns hold
time to ensure proper timing at the receiver.)
From 0.3VDD to 0.7VDD
Min.
0
4.0
4.7
4.0
250
0
From 0.7VDD to 0.3VDD
4.0
4.7
Typ.
Max.
100
1000
300
50
Unit
kHz
µs
µs
µs
ns
ns
ns
ns
µs
µs
ns
Ordering Information
Ordering Code
Freq. Mask
Code
W48S87
72
Document #: 38-00855-*A
Package
Name
H
X
Package Type
48-pin SSOP (300 mils)
48-pin TSSOP
17
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