MC14508BCL 查看數據表（PDF） - Motorola => Freescale

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MC14508BCL

Dual 4-Bit Latch

Motorola => Freescale 

3–STATE MODE OF OPERATION

The MC14508B can be used in bussed systems as shown.

The output terminals of N 4–bit latches can be directly wired

to a bus line, and to one of the 4–bit latches selected. The

selected latch controls the logic state of the bus line and the

remaining (N–1) 4–bit latches are disabled into a high imped-

ance “off” state. The number of latches, N, which may be

connected to a bus line is determined from the output drive

current, IOD, the 3–state or disabled output leakage current,

ITL, and the load current, IL, required to drive the bus line (in-

cluding fanout to other device inputs) and can be calculated

by the following:

N = IOD – IL + 1

ITL

N must be calculated for both high and low logic states of the

bus line.

IOD

SELECTED AS

1/2

DRIVING DEVICE MC14508B

IOD

ITL

1/2

DISABLED MC14508B

ITL

ITL

DISABLED

1/2

MC14508B

TYPICAL 3–STATE APPLICATIONS

EXAMPLE 1

RESET

CLOCK

SERIAL

DATA

MC14015B

4–BIT SHIFT

4–BIT SHIFT

REGISTER

REGISTER

STROBE

DISABLE

MC

QUAD LATCH 14508B

(3–STATE)

QUAD LATCH

(3–STATE)

DISABLE

4–LINE DATA BUS

ITL IL

IL

BUS LINES

EXAMPLE 2

3–STATE

4–BIT LATCH

3–STATE

4–BIT LATCH

MC

14508B

MC

14508B

4–LINE DATA BUS

4–LINE DATA BUS

3–STATE

4–BIT LATCH

3–STATE

4–BIT LATCH

DATA BUS

MC14519B

A

B

MC14508B

348

MOTOROLA CMOS LOGIC DATA

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