LC72134M 查看數據表（PDF） - SANYO -> Panasonic

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LC72134M

Dual PLL Frequency Synthesizer for FM Tuner Systems

SANYO -> Panasonic 

LC72134M

DI Control Data

No. Control block/data

Function

Related data

• Specifies the divider for the main PLL programmable divider.

This is a binary value in which P15 is the MSB. The position of the LSB changes depending on DVS and

SNS.

(* : don’t care)

DVS

SNS

LSB Set divisor (N)

Actual divisor

1

*

P0

272 to 65535 Twice the set value

0

1

P0

272 to 65535

The set value

Main PLL

0

0

P4

4 to 4095

The set value

1

programmable

divider data

* LSB: When P4 is the LSB, P0 to P3 are ignored.

P0 to P15

• These pins select the signal input to the main PLL programmable divider (FMINa or AMIN) and switch the

DVS, SNS

input frequency range.

(* : don’t care)

DVS

1

0

0

SNS

*

1

0

Input pin Frequency range accepted by the input pin

FMINa

10 to 160 MHz

AMIN

2 to 40 MHz

AMIN

0.5 to 10 MHz

* See the “Structure of the Programmable Divider” section for details.

• Selects the reference frequency for the main PLL

Main PLL reference

divider data

R0 to R3

2

R3 R2 R1 R0

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Reference frequency

100 kHz

50

25

25

12.5

6.25

3.125

3.125

10

9

5

1

3

15

PLL INHIBIT + X’tal OSC STOP

PLL INHIBIT

* PLL INHIBIT mode

In this mode, the main PLL programmable divider is stopped, the FMINa and AMIN pins are pulled down

to ground, and the main PLL charge pump output goes to the high-impedance state.

* Crystal oscillator stop mode

The crystal oscillator circuit is stopped.

XS

Therefore applications must not select this mode while the sub PLL is operating.

• Crystal oscillator element selection data

XS = 0: 4.5 MHz

XS = 1: 7.2 MHz

Note that 7.2 MHz is selected after a power on reset.

Continued on next page.

No. 5814-10/27

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