LC72134M 查看數據表（PDF） - SANYO -> Panasonic

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LC72134M

Dual PLL Frequency Synthesizer for FM Tuner Systems

SANYO -> Panasonic 

LC72134M

Continued from preceding page.

Pin Pin No.

Type

Function

IFIN1

• IFIN1 is selected when LCTS in the serial data is set to 0.

• The input frequency range is 0.4 to 25 MHz when IFS is 1, and 0.4 to 12 MHz

15

IF counter 1

when IFS is 0.

• The signal is passed directly to the IF counter.

• The result is output, MSB first, through the DO pin.

• Four measurement periods are supported: 4, 8, 32, and 64 ms.

IFIN2/I1

13

FMINb

12

IF counter 2

input port

• IFIN2 is selected when both LCTS and L/I1 in the serial data are set to 1.

• The input frequency range is 0.4 to 25 MHz when IFS is 1 and 0.4 to 12 MHz

when IFS is 0.

• The signal is passed directly to the IF counter.

• The result (the IF counter value) is output, MSB first, through the DO pin.

• Four measurement periods are supported: 4, 8, 32, and 64 ms.

• If the L/I1 bit in the serial data is set to 0, the IFIN2/I1 port will function as an input

port and the state of the input pin will be reported to the microcontroller from the

DO pin. (Note that the LCTS value is ignored in this case.)

When the input state is low: the data will be 0:

When the input state is high: the data will be 1:

Sub PLL local

oscillator

signal input

• FMINb is selected when SDVS in the serial data is set to 1.

• The input frequency range is 10 to 160 MHz.

• The signal is passed through an internal divide-by-two prescaler and then input to

the swallow counter.

• The divisor can be set to a value in the range 272 to 8191. Since the internal

divide-by-two prescaler is used, the actual divisor will be twice the set value.

• FMINb goes to the stopped state (pulled down) when SDVS in the serial data is

set to 0.

• Sub PLL charge pump output

Sub PLL

A high level is output from the PD pin when the frequency of the local oscillator

PDb

11

charge pump signal divided by N is higher than the reference frequency, and a low level is

output

output when that frequency is lower. This pin goes to the high-impedance state

when the frequencies match.

Equivalent circuit

AINb

Sub PLL low-

10

pass filter

• Connections for the n-channel MOS transistor used for the sub PLL active low-

AOUTb

9

amplifier

transistor

pass filter.

No. 5814-7/27

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