AD9430BSVZ-170 查看數據表（PDF） - Analog Devices

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AD9430BSVZ-170

12-Bit, 170/210 MSPS 3.3 V A/D Converter

Analog Devices 

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AD9430

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

S5 1

DNC 2

S4 3

AGND 4

S2 5

S1 6

DNC 7

AVDD 8

AGND 9

SENSE 10

VREF 11

AGND 12

AGND 13

AVDD 14

AVDD 15

AGND 16

AGND 17

AVDD 18

AVDD 19

AGND 20

VIN+ 21

VIN– 22

AGND 23

AVDD 24

AGND 25

PIN 1

AD9430

CMOS PINOUT

TOP VIEW

(Not to Scale)

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

75 DRVDD

74 DRGND

73 DA4

72 DA3

71 DA2

70 DA1

69 DA0

68 DNC

67 DRGND

66 DNC

65 DNC

64 DCO+

63 DCO–

62 DRVDD

61 DRGND

60 OR_B

59 DB11

58 DB10

57 DB9

56 DB8

55 DB7

54 DRVDD

53 DRGND

52 DB6

51 DB5

NOTES

1. THE AD9430 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF

THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF

THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL

TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE

SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE

DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.

Figure 4. CMOS Dual-Mode Pin Configuration

Table 7. CMOS Mode Pin Function Descriptions

Pin Number

1

2, 7, 42, 43, 65, 66, 68

3

4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 35, 38, 41, 86,

87, 91, 92, 93, 96, 97, 100

5

6

8, 14, 15, 18, 19, 24, 27, 28, 29, 34, 39, 40, 88, 89, 90, 94,

95, 98, 99

10

11

21

22

32

33

Mnemonic

S5

DNC

S4

AGND1

Description

Full-Scale Adjust Pin. AVDD sets fS = 0.768 V p-p differential,

GND sets fS = 1.536 V p-p differential.

Do Not Connect.

Interleaved, Parallel Select Pin. High = interleaved.

Analog Ground.

S2

S1

AVDD

Output Mode Select. Low = dual-port CMOS, high = LVDS.

Data Format Select. Low = binary, high = twos complement for

both CMOS and LVDS modes.

3.3 V Analog Supply.

SENSE

Reference Mode Select Pin. Float for internal reference operation.

VREF

1.235 V Reference I/O—Function Dependent on SENSE.

VIN+

Analog Input—True.

VIN–

Analog Input—Complement.

DS+

Data Sync (Input)—True. Tie low if not used.

DS–2

Data Sync (Input)—Complement. Tie high if not used.

Rev. E | Page 11 of 44

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