HEF4043B 查看數據表（PDF） - NXP Semiconductors.
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HEF4043B Datasheet PDF : 13 Pages
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NXP Semiconductors
HEF4043B
Quad R/S latch with 3-state outputs
6.2 Pin description
Table 2. Pin description
Symbol
Pin
1Q to 4Q
2, 9, 10, 1
1R to 4R
3, 7, 11, 15
1S to 4S
4, 6, 12, 14
OE
5
VSS
8
n.c.
13
VDD
16
7. Functional description
Description
3-state buffered latch output
reset input (active HIGH)
set input (active HIGH)
common output enable input
ground supply voltage
not connected
supply voltage
Table 3. Function table[1]
Inputs
OE
nS
nR
L
X
X
H
L
H
H
H
X
H
L
L
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high impedance state.
8. Limiting values
Output
nQ
Z
L
H
latched
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VDD
VI
IIK
IOK
II/O
Tstg
Tamb
Ptot
supply voltage
input voltage
input clamping current
output clamping current
input/output current
storage temperature
ambient temperature
total power dissipation
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
Tamb −40 °C to +85 °C
DIP16 package
SO16 package
P
power dissipation
per output
Min
−0.5
−0.5
-
-
-
−65
−40
[1] -
[2] -
-
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.
Max
Unit
+18
V
VDD + 0.5 V
±10
mA
±10
mA
±10
mA
+150
°C
+85
°C
750
mW
500
mW
100
mW
HEF4043B_6
Product data sheet
Rev. 06 — 11 November 2008
© NXP B.V. 2008. All rights reserved.
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