HEF4043B 查看數據表（PDF） - NXP Semiconductors.
零件编号
产品描述 (功能)
比赛名单
HEF4043B Datasheet PDF : 13 Pages
| |||
NXP Semiconductors
HEF4043B
Quad R/S latch with 3-state outputs
VI 90 %
tW
negative
pulse
VM
10 %
0V
tf
VI
positive
pulse
tr
90 %
VM
10 %
0V
tW
VM
tr
tf
VM
VI
G
VDD
VO
DUT
VEXT
RL
RT
CL
RL
001aai546
Fig 6.
Test and measurement data is given in Table 10.
Definitions test circuit:
DUT = Device Under Test.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Test circuit for measuring switching times
Table 10. Test data
Supply voltage
5 V to 15 V
Input
VI
VDD
tr, tf
≤ 20 ns
Load
CL
50 pF
RL
1 kΩ
VEXT
tPLH, tPHL
open
tPLZ, tPZL
2VDD
tPHZ, tPZH
GND
HEF4043B_6
Product data sheet
Rev. 06 — 11 November 2008
© NXP B.V. 2008. All rights reserved.
8 of 13
Share Link: 