ADSP-21MSP58BST-104 查看數據表（PDF） - Analog Devices

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ADSP-21MSP58BST-104

DSP Microcomputers

Analog Devices 

ADSP-21msp58/59

SPORT1 SCLKDIV

Serial Clock Divide Modulus

0x3FF1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SPORT1 RFSDIV

Receive Frame Sync Divide Modulus

0x3FF0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Analog Autobuffer/Powerdown Control Register

0x3FEF

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000

00

XTALDIS

XTAL Pin Disable During Powerdown

1 = disabled, 0 = enabled

(XTAL pin should be disabled when

no external crystal is connected)

XTALDELAY

Delay Startup From Powerdown 4096 Cycles

1 = delay, 0 = no delay

(use delay to let internal phase locked

loop or external oscillator stabilize)

PDFORCE

Powerdown Force

1 = force processor to vector to

powerdown interrupt

PUCR

Powerup Context Reset

1 = soft reset, 0 = resume execution

ARBUF

ADC Receive Autobuffer Enable

ATBUF

DAC Transmit Autobuffer Enable

ARMREG

Receive M Register

ARIREG

Receive I Register

ATMREG

Transmit M Register

ATIREG

Transmit I Register

HMASK Register

0x3FE8

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000000000000000

Host HDR5 Read

Host HDR4 Read

Host HDR3 Read

Host HDR2 Read

Host HDR1 Read

Host HDR0 Read

Interrupt Enables

1 = Enable

0 = Disable

Host HDR0 Write

Host HDR1 Write

Host HDR2 Write

Host HDR3 Write

Host HDR4 Write

Host HDR5 Write

Control Registers

REV. 0

–15–

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