ADSP-21MSP58BST-104 查看數據表（PDF） - Analog Devices

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ADSP-21MSP58BST-104

DSP Microcomputers

Analog Devices 

ADSP-21msp58/59

HSR6

0x3FE6

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000000000000000

ADSP-21msp58/59 HDR5 Write

ADSP-21msp58/59 HDR4 Write

ADSP-21msp58/59 HDR3 Write

ADSP-21msp58/59 HDR2 Write

ADSP-21msp58/59 HDR1 Write

ADSP-21msp58/59 HDR0 Write

Host HDR0 Write

Host HDR1 Write

Host HDR2 Write

Host HDR3 Write

Host HDR4 Write

Host HDR5 Write

HSR7

0x3FE7

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0000000010000000

Control Registers

ADSP-21msp58/59 HDR0 Write

ADSP-21msp58/59 HDR1 Write

ADSP-21msp58/59 HDR2 Write

ADSP-21msp58/59 HDR3 Write

ADSP-21msp58/59 HDR4 Write

ADSP-21msp58/59 HDR5 Write

Overwrite Mode

Software Reset

INSTRUCTION SET DESCRIPTION

The ADSP-21msp58/59 assembly language instruction set has

an algebraic syntax that was designed for ease of coding and

readability. The assembly language, which takes full advantage

of the processor’s unique architecture, offers the following

benefits:

• The algebraic syntax eliminates the need to remember cryptic

assembler mnemonics. For example, a typical arithmetic add

instruction, such as AR = AX0 + AY0, resembles a simple

equation.

• Every instruction assembles into a single 24-bit word and

executes in a single cycle.

•The syntax is a superset of the ADSP-2100 Family assembly

language and is completely source and object code compatible

with other family members. Programs may, however, need to

be relocated to utilize internal memory and conform to the

ADSP-21msp58/59 interrupt vector and reset vector map.

• Sixteen condition codes are available. For conditional jump,

call, return, or arithmetic instructions, the condition can be

checked and the operation executed in the same instruction

cycle.

• Multifunction instructions allow parallel execution of an

arithmetic instruction with up to two fetches and one write to

processor memory space during a single instruction cycle.

Consult the ADSP-2100 Family User’s Manual for a complete

description of the syntax and an instruction set reference.

ADSP-21msp58/59 EXTENDED INSTRUCTION SET

The ADSP-21msp58/59 has a number of additional instruc-

tions beyond the standard ADSP-2100 Family instruction set.

These additional instructions and mathematical operations are

described below.

Slow IDLE

Slow IDLE allows slowing the processor’s internal clock by a

factor of 16, 32, 64, or 128 during IDLE. The instruction

source code is specified as follows:

Syntax: IDLE (n);

Permissible Values for n

16, 32, 64, 128

Examples: IDLE;

IDLE (16);

Description: The IDLE instruction causes the processor to

wait indefinitely in a low power state until an in-

terrupt occurs. When an unmasked interrupt oc-

curs, it is serviced; execution then continues with

the instruction following the IDLE instruction.

The optional value provides a “slow idle” fea-

ture; slowing the clock down by the factor set

with the value.

Interrupt Enable and Disable Instructions

The ADSP-21msp58/59 supports an interrupt enable instruc-

tion and interrupt disable instruction. Interrupts are enabled by

default at reset. The interrupt enable instruction source code is

specified as follows:

REV. 0

–17–

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